公开(公告)号：US06455378B1

公开(公告)日：2002-09-24

申请号：US09695036

申请日：2000-10-25

Applicant: Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

Inventor： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC: H01L21336

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7808 ,  H01L29/7811 ,  Y10S438/981

Abstract: There are formed a gate insulator 8 and a gate 3 of a power transistor Q having a trench-gate structure. There are then formed a channel region 5 and a source region 6 of the power transistor Q.

Abstract translation: 形成具有沟槽栅结构的功率晶体管Q的栅极绝缘体8和栅极3。 然后形成功率晶体管Q的沟道区域5和源极区域6。

公开(公告)号：US20120193702A1

公开(公告)日：2012-08-02

申请号：US13361010

申请日：2012-01-30

Applicant: Nobuo Machida ,  Koichi Arai

Inventor： Nobuo Machida ,  Koichi Arai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068

Abstract: In a SiC-based MISFET and a manufacturing process thereof, after the introduction of an impurity, extremely-high-temperature activation annealing is required. Accordingly, it is difficult to frequently use a self-alignment process as performed in a silicon-based MISFET manufacturing process. This results in the problem that, to control the characteristics of a device, a high-accuracy alignment technique is indispensable. In accordance with the present invention, in a semiconductor device such as a SiC-based vertical power MISFET using a silicon-carbide-based semiconductor substrate and a manufacturing method thereof, a channel region, a source region, and a gate structure are formed in mutually self-aligned relation.

Abstract translation: 在基于SiC的MISFET及其制造方法中，在引入杂质之后，需要极高温的活化退火。 因此，难以频繁地使用在硅系MISFET制造工序中进行的自对准工序。 这导致了为了控制装置的特性，高精度对准技术是必不可少的问题。 根据本发明，在诸如使用碳化硅基半导体衬底的基于SiC的垂直功率MISFET等半导体器件及其制造方法中，形成沟道区，源极区和栅极结构 相互自我约束的关系

公开(公告)号：US20120142156A1

公开(公告)日：2012-06-07

申请号：US13396816

申请日：2012-02-15

Applicant: Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

Inventor： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC: H01L21/8234

CPC classification number: H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract translation: 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US07910990B2

公开(公告)日：2011-03-22

申请号：US12868698

申请日：2010-08-25

Applicant: Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

Inventor： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC: H01L29/78

CPC classification number: H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract translation: 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US20090294845A1

公开(公告)日：2009-12-03

申请号：US12539383

申请日：2009-08-11

Applicant: HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

Inventor： HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract translation: 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US20080153235A1

公开(公告)日：2008-06-26

申请号：US12037139

申请日：2008-02-26

Applicant: Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

Inventor： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC: H01L21/8234

CPC classification number: H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract translation: 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US20070117329A1

公开(公告)日：2007-05-24

申请号：US11653404

申请日：2007-01-16

Applicant: Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

Inventor： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC: H01L21/336

CPC classification number: H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

公开(公告)号：US07189621B2

公开(公告)日：2007-03-13

申请号：US10986495

申请日：2004-11-12

Applicant: Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

Inventor： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC: H01L21/336

CPC classification number: H01L29/7808 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. In this method, a trench wherein a trench-gate is to be formed is formed on the main surface of the semiconductor substrate with the insulating film formed thereon with a mask; and the side surface of the insulating film is caused to retreat from the upper end of the trench by isotropic etching, whereby a gate insulating film and a conductive layer to be the trench gate are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. According to the present invention, occurrence of a source offset and damage of a gate insulating film can be prevented.

Abstract translation: 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 形成比半导体衬底的主表面高的沟槽栅极导电层，并且沟槽栅极导电层和栅极绝缘膜形成在沟槽的周围的沟槽中并在半导体衬底的主表面上方。 在该方法中，在其上形成有绝缘膜的半导体衬底的主表面上形成有要形成沟槽栅的沟槽; 并且通过各向同性蚀刻使绝缘膜的侧表面从沟槽的上端退回，由此在沟槽中并在半导体的主表面上形成作为沟槽栅极的栅极绝缘膜和导电层 衬底在沟槽的周边。 根据本发明，可以防止源极偏移的发生和栅极绝缘膜的损坏。

公开(公告)号：US07151035B2

公开(公告)日：2006-12-19

申请号：US10511541

申请日：2002-04-16

Applicant: Makoto Koshimizu ,  Yasuaki Kagotoshi ,  Nobuo Machida

Inventor： Makoto Koshimizu ,  Yasuaki Kagotoshi ,  Nobuo Machida

IPC: H01L21/331

CPC classification number: H01L29/66242 ,  B29C45/12 ,  B29C45/32 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/7378

Abstract: A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so as to protrude from a surface opposite to a semiconductor substrate 1 toward a main surface of the semiconductor substrate 1 in the base extraction electrode 5B, and protruded length thereof is set to be equal to or smaller than one half of thickness of the insulation film 4 interposed between the main surface of the semiconductor substrate 1 and a lower surface of the base extraction electrode 5B.

Abstract translation: 侧壁绝缘膜9设置在形成在异质结双极晶体管的基极引出电极5B中的第一开口部分8a的侧表面上，并且侧壁绝缘膜9的一部分延伸以突出 从与半导体衬底1相对的表面朝向基极引出电极5B中的半导体衬底1的主表面，并且其突出长度被设置为等于或小于插入在绝缘膜4之间的绝缘膜4的厚度的一半 半导体衬底1的主表面和基极引出电极5B的下表面。

公开(公告)号：US20050181569A1

公开(公告)日：2005-08-18

申请号：US10511541

申请日：2002-04-16

Applicant: Makoto Koshimizu ,  Yasuaki Kagotoshi ,  Nobuo Machida

Inventor： Makoto Koshimizu ,  Yasuaki Kagotoshi ,  Nobuo Machida

IPC: B29C45/12 ,  B29C45/32 ,  H01L21/331 ,  H01L29/08 ,  H01L29/72 ,  H01L29/737 ,  H01L29/732 ,  H01L21/8222 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/66242 ,  B29C45/12 ,  B29C45/32 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/7378

Abstract: A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so as to protrude from a surface opposite to a semiconductor substrate 1 toward a main surface of the semiconductor substrate 1 in the base extraction electrode 5B, and protruded length thereof is set to be equal to or smaller than one half of thickness of the insulation film 4 interposed between the main surface of the semiconductor substrate 1 and a lower surface of the base extraction electrode 5B.

Abstract translation: 侧壁绝缘膜9设置在形成在异质结双极晶体管的基极引出电极5B中的第一开口部分8a的侧表面上，并且侧壁绝缘膜9的一部分延伸以突出 从与半导体衬底1相对的表面朝向基极引出电极5B中的半导体衬底1的主表面，并且其突出长度被设置为等于或小于插入在绝缘膜4之间的绝缘膜4的厚度的一半 半导体衬底1的主表面和基极引出电极5B的下表面。