公开(公告)号：US08299495B2

公开(公告)日：2012-10-30

申请号：US13014599

申请日：2011-01-26

申请人： Hiroshi Inagawa

发明人： Hiroshi Inagawa

IPC分类号： H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/66348

摘要： In a reverse conducting IGBT, diode cathode regions are formed dispersedly on the back side of a device chip. When the distribution density of the diode cathode region becomes low, VF of a fly-back diode, that is, a forward voltage drop becomes large. On the other hand, when the distribution density of the diode cathode region becomes high, it becomes hard for a PN junction at a collector part to turn ON and a snap back occurs. In contrast to this, there is a method of providing about one to several diode cathode absent regions having a macro area, however, the arrangement of the regions itself directly affects the device characteristics, and therefore, it is difficult to control the device characteristics and variations thereof.In the present invention, dot-shaped diode cathode regions on the back side of the device chip are distributed into the shape of a substantially uniform XY lattice and at the same time, the lattice constant in a Y direction is made longer than that in an X direction in parallel with a linear gate electrode in a reverse conducting IGBT having a large number of the linear gate electrodes.

摘要翻译： 在反向导通IGBT中，二极管阴极区分散地形成在器件芯片的背面。 当二极管阴极区域的分布密度变低时，回扫二极管的VF即正向压降变大。 另一方面，当二极管阴极区域的分布密度变高时，集电体部分的PN结变得难以接通并发生卡接。 与此相反，存在提供大约一至几个具有宏区域的二极管阴极不存在区域的方法，然而，区域本身的布置直接影响器件特性，因此难以控制器件特性和 其变体。 在本发明中，器件芯片背面的点状二极管阴极区分布成基本均匀的XY晶格的形状，同时Y方向的晶格常数比 X方向与具有大量线性栅电极的反向导通IGBT中的线性栅电极并联。

公开(公告)号：US08168498B2

公开(公告)日：2012-05-01

申请号：US12962499

申请日：2010-12-07

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

公开(公告)号：US20110076818A1

公开(公告)日：2011-03-31

申请号：US12962499

申请日：2010-12-07

申请人： HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

发明人： HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

摘要翻译： 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US07910985B2

公开(公告)日：2011-03-22

申请号：US12759858

申请日：2010-04-14

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L29/76

CPC分类号： H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 沟槽栅极导电层形成为等于或高于半导体衬底的主表面。 此外，沟槽栅极的导电层形成为具有基本上平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 此外，在蚀刻半导体衬底以形成等于或高于半导体衬底的主表面的沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区和源极区。 根据本发明制造的半导体器件不会产生源极偏移。

公开(公告)号：US20100320533A1

公开(公告)日：2010-12-23

申请号：US12868698

申请日：2010-08-25

申请人： HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

发明人： HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L29/78

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

摘要翻译： 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体衬底的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US07214558B2

公开(公告)日：2007-05-08

申请号：US11257060

申请日：2005-10-25

申请人： Atsushi Kurokawa ,  Hiroshi Inagawa ,  Toshiaki Kitahara ,  Yoshinori Imamura

发明人： Atsushi Kurokawa ,  Hiroshi Inagawa ,  Toshiaki Kitahara ,  Yoshinori Imamura

IPC分类号： H01L21/00 ,  H01L21/8235

CPC分类号： H01L29/66318 ,  H01L29/0657 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/7371

摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.

摘要翻译： 提供了改进双极晶体管的性质的技术。 具体地说，通过剥离法在基台周围形成集电极时，在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜， 随后在衬底的整个表面上依次形成金锗（AuGe），镍（Ni）和Au，使得它们的堆叠膜不会变成隔离图案。 结果，基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面4a上的剥离。 此外，通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻，或 n型InGaAs层。

公开(公告)号：US06858896B2

公开(公告)日：2005-02-22

申请号：US10046077

申请日：2002-01-16

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L27/06 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/06 ,  H01L29/12 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78 ,  H01L21/76

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

公开(公告)号：US06818949B2

公开(公告)日：2004-11-16

申请号：US10750819

申请日：2004-01-05

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Ooishi

IPC分类号： H01L2976

CPC分类号： H01L29/7808 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

摘要： Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. In this method, a trench wherein a trench-gate is to be formed is formed on the main surface of the semiconductor substrate with the insulating film formed thereon with a mask; and the side surface of the insulating film is caused to retreat from the upper end of the trench by isotropic etching, whereby a gate insulating film and a conductive layer to be the trench gate are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. According to the present invention, occurrence of a source offset and damage of a gate insulating film can be prevented.

摘要翻译： 描述了一种用于制造半导体器件的方法，该半导体器件具有通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得的沟槽栅极结构的FET，其中， 形成比半导体衬底的主表面高的沟槽栅极导电层，并且沟槽栅极导电层和栅极绝缘膜形成在沟槽的周围的沟槽中并在半导体衬底的主表面上方。 在该方法中，在其上形成有绝缘膜的半导体衬底的主表面上形成有要形成沟槽栅的沟槽; 并且通过各向同性蚀刻使绝缘膜的侧表面从沟槽的上端退回，由此在沟槽中并在半导体的主表面上形成作为沟槽栅极的栅极绝缘膜和导电层 衬底在沟槽的周边。 根据本发明，可以防止源极偏移的发生和栅极绝缘膜的损坏。

公开(公告)号：US06649458B2

公开(公告)日：2003-11-18

申请号：US10347806

申请日：2003-01-22

申请人： Atsushi Kurokawa ,  Toshiaki Kitahara ,  Hiroshi Inagawa ,  Yoshinori Imamura

发明人： Atsushi Kurokawa ,  Toshiaki Kitahara ,  Hiroshi Inagawa ,  Yoshinori Imamura

IPC分类号： H01L21338

CPC分类号： H01L29/66143 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0652 ,  H01L27/0658 ,  H01L27/0664 ,  H01L29/475 ,  H01L29/66212 ,  H01L29/66318 ,  H01L29/7371

摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.

摘要翻译： 本发明在具有异质结双极晶体管（HBT），肖特基二极管和电阻元件的半导体器件的制造方法中实现了制造成品率的提高和制造成本的降低。 本发明涉及一种半导体器件的制造方法，其中，在半导体器件的一个表面上依次形成成为副集电极层，集电极层，基极层，宽间隙发射极层和发射极层的各个半导体层 半导体衬底，然后处理各个半导体层以形成异质结双极晶体管，肖特基二极管和电阻元件。 使用相同的材​​料（例如WSiN）同时形成异质结双极晶体管的发射极，肖特基二极管的肖特基电极和电阻元件的电阻膜。 因此，可以减少工时，并且可以降低半导体器件的制造成本。

公开(公告)号：US06455378B1

公开(公告)日：2002-09-24

申请号：US09695036

申请日：2000-10-25

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7808 ,  H01L29/7811 ,  Y10S438/981

摘要： There are formed a gate insulator 8 and a gate 3 of a power transistor Q having a trench-gate structure. There are then formed a channel region 5 and a source region 6 of the power transistor Q.

摘要翻译： 形成具有沟槽栅结构的功率晶体管Q的栅极绝缘体8和栅极3。 然后形成功率晶体管Q的沟道区域5和源极区域6。