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    SURROGATE MODELING OF MOLTEN DROPLET COALESCENCE IN ADDITIVE MANUFACTURING
    32.
    发明公开
    SURROGATE MODELING OF MOLTEN DROPLET COALESCENCE IN ADDITIVE MANUFACTURING 审中-公开

    公开(公告)号：US20240017325A1

    公开(公告)日：2024-01-18

    申请号：US17864082

    申请日：2022-07-13

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Søren Taverniers ,  Morad Behandish ,  Svyatoslav Korneev

    IPC: B22F10/85 ,  B22F10/22 ,  B33Y50/02

    CPC classification number: B22F10/85 ,  B22F10/22 ,  B33Y50/02

    Abstract: Techniques for modeling a droplet-based additive manufacturing process are disclosed. An example method includes obtaining training data, setting one or more hyperparameter values in a data-driven surrogate model architecture, and training, by a processing device, the surrogate model architecture on the training data to generate a trained surrogate model. The trained surrogate model is to be used in lieu of a physics-based model to make predictions about the results of an additive manufacturing process. The training data includes pairs of input data and output data, wherein the input data describes an initial state of a substrate and a molten droplet inside a moving subdomain prior to the molten droplet impacting the substrate and the output data describes a final state of the substrate inside that moving subdomain after the molten droplet has impacted the substrate and coalesced with previously deposited droplets making up the initial state of the substrate.

    HYBRID SOLVER FOR INTEGRATED CIRCUIT DIAGNOSTICS AND TESTING
    34.
    发明公开
    HYBRID SOLVER FOR INTEGRATED CIRCUIT DIAGNOSTICS AND TESTING 审中-公开

    公开(公告)号：US20240003970A1

    公开(公告)日：2024-01-04

    申请号：US17855012

    申请日：2022-06-30

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Aleksandar B. Feldman ,  Johan de Kleer ,  Alexandre Campos Perez ,  Ion Matei

    IPC: G01R31/3183 ,  G01R31/317

    CPC classification number: G01R31/318307 ,  G01R31/31704 ,  G01R31/318314

    Abstract: One embodiment provides a method and a system for computing diagnoses for a physical system. During operation, the system can obtain a design of the physical system, generate a design of a diagnostic system by augmenting the design of the physical system based on a number of fault-emulating subsystems, and convert the design of the diagnostic system into a polynomial formula comprising a plurality of variables. The plurality of variables can include inputs and outputs of the original physical system and a number of ancillary variables. The system can further embed the polynomial formula on a hardware-based solver configured to perform optimization using the polynomial formula as an objective function to obtain a diagnostic vector used for explaining faults in the physical system.

    Polarization controlled transistor
    35.
    发明授权
    Polarization controlled transistor 有权

    公开(公告)号：US11848371B2

    公开(公告)日：2023-12-19

    申请号：US16920249

    申请日：2020-07-02

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Thomas Wunderer ,  Jengping Lu ,  Noble M. Johnson

    IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

    CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7788

    Abstract: A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction.

    METHODS AND SYSTEMS OF GEOMETRIC REPRESENTATION GENERATION BASED ON A SYSTEM-LEVEL MODEL
    37.
    发明公开
    METHODS AND SYSTEMS OF GEOMETRIC REPRESENTATION GENERATION BASED ON A SYSTEM-LEVEL MODEL 审中-公开

    公开(公告)号：US20230394191A1

    公开(公告)日：2023-12-07

    申请号：US17831125

    申请日：2022-06-02

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Randi Wang ,  Anurag Bhattacharyya ,  Qian Ye ,  Clinton Morris ,  Amirmassoud Mirzendehdel ,  Morad Behandish

    IPC: G06F30/18

    CPC classification number: G06F30/18 ,  G06F2111/04

    Abstract: This disclosure provides techniques for automatically generating a geometric representation based on a system-level model (e.g., a lumped parameter model, or LPM). The geometric representation may include a three-dimensional (3D) or cross-sectional shape, resulting from topology optimization within a design space automatically generated without human intervention. An example method may include identifying one or more constraints for each of two or more components of an LPM. One or more conditions are generated for the LPM. The one or more conditions are mapped to the one or more constraints. A processing device may generate a design space for a geometric representation to perform functions represented by the LPM. The geometric representation is subject to the generated one or more conditions. The processing device may then perform topology optimization of the geometric representation in the design space to generate an optimized geometry (e.g., a converged and/or final output).

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