公开(公告)号：US20080104164A1

公开(公告)日：2008-05-01

申请号：US11586810

申请日：2006-10-26

Applicant: Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

IPC: G06F7/52

CPC classification number: G06F7/5324 ,  G06F2207/3828

Abstract: A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

Abstract translation: 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

公开(公告)号：US20080098278A1

公开(公告)日：2008-04-24

申请号：US11540346

申请日：2006-09-29

Applicant: Sanu Mathew ,  Vishak Venkatraman ,  Steven K. Hsu ,  Ram Krishnamurthy

Inventor： Sanu Mathew ,  Vishak Venkatraman ,  Steven K. Hsu ,  Ram Krishnamurthy

IPC: G11C29/00

CPC classification number: G11C7/1006 ,  G06F7/533 ,  G06F7/5332 ,  G06F7/5334 ,  G06F7/74

Abstract: For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that is encoded for partial product reduction, and second circuitry to generate a product based at least in part on the encoded data and on data corresponding to a second number. Other embodiments are also disclosed.

Abstract translation: 对于一个公开的实施例，装置包括至少部分地基于对应于第一号码的地址从可寻址位置输出编码数据的第一电路，其中编码数据至少部分地基于对应于第一号码的数据 并且其被编码用于部分产品减少，以及第二电路，用于至少部分地基于编码数据和对应于第二数量的数据来生成产品。 还公开了其他实施例。

公开(公告)号：US20070203961A1

公开(公告)日：2007-08-30

申请号：US11242573

申请日：2005-09-30

Applicant: Sanu Mathew ,  David Harris ,  Ram Krishnamurthy

Inventor： Sanu Mathew ,  David Harris ,  Ram Krishnamurthy

IPC: G06J1/00

CPC classification number: G06F7/728 ,  G06F5/01

Abstract: Embodiments of apparatuses and methods for multiplicand shifting in a linear systolic array modular multiplier are disclosed. In one embodiment, an apparatus includes two processing elements of a linear systolic array. One processing element includes multiplication logic, multiplicand shift logic, an adder, modulus logic, and modulus shift logic. The multiplication logic is to multiply a word of the multiplicand and a bit of the multiplier to generate a product. The multiplicand shift logic is to shift the word of the multiplicand. The adder is to add the product to a first running sum to generate a second running sum. The modulus logic is to conditionally add a word of a modulus and the second running sum. The modulus shift logic is to shift the word of the modulus. The next processing element includes logic to multiply the shifted word of the multiplicand and the next bit of the multiplier.

Abstract translation: 公开了在线性收缩阵列模数乘法器中被乘数移位的装置和方法的实施例。 在一个实施例中，装置包括线性收缩阵列的两个处理元件。 一个处理元件包括乘法逻辑，被乘数移位逻辑，加法器，模数逻辑和模移位逻辑。 乘法逻辑是将被乘数的一个乘法和一个乘法器的乘法乘以产生乘积。 被乘数移位逻辑是移位被乘数的字。 加法器将产品加到第一个运行总和以产生第二个运行总和。 模数逻辑是有条件地添加一个单词的模数和第二个运行总和。 模数移位逻辑是移动模数的单词。 下一个处理元件包括用于乘法被乘数的移位的字和乘法器的下一位的逻辑。

公开(公告)号：US20070146013A1

公开(公告)日：2007-06-28

申请号：US11321328

申请日：2005-12-28

Applicant: Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

Inventor： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC: H03K19/094

CPC classification number: H03K19/0963 ,  G01R31/3008 ,  G01R31/31721 ,  H03K19/00361 ,  H03K19/00384

Abstract: Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.

Abstract translation: 这里公开了用于向动态逻辑电路提供自适应保持器功能的解决方案。 在一些实施例中，可编程保持器电路耦合到寄存器文件电路。 包括泄漏指示器电路，用于在寄存器文件的至少一部分中建模泄漏。 控制电路耦合到泄漏指示器电路和可编程保持器电路，以根据建模的泄漏来控制保持器强度。 要求保护或以其他方式公开其他实施例。

公开(公告)号：US07196548B2

公开(公告)日：2007-03-27

申请号：US10927574

申请日：2004-08-25

Applicant: Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

Inventor： Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC: H03K19/094 ,  H03K17/16

CPC classification number: H03K3/356156 ,  H03K3/356191

Abstract: A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

Abstract translation: 本文描述了具有新颖的静态无功接收器电路的单端电流感测总线。 在一个实施例中，接收器电路示例包括锁存电路，以在响应于输入的评估阶段期间锁存第一输出和第二输出的值;耦合到锁存电路的预充电电路以预充电锁存电路 以及耦合到预充电电路和锁存电路的静态功耗阻塞（SPDB）电路，以在预充电阶段期间基本上阻止静态功率消散。 还描述了其它方法和装置。

公开(公告)号：US07132849B2

公开(公告)日：2006-11-07

申请号：US10852586

申请日：2004-05-24

Applicant: John Tucker ,  Ram Krishnamurthy ,  John James Paulos

Inventor： John Tucker ,  Ram Krishnamurthy ,  John James Paulos

IPC: G06F7/38 ,  G06F17/50 ,  H03K19/173 ,  H03K19/00

CPC classification number: H03K19/1731

Abstract: Method and apparatus for configuring the operation of an integrated circuit. An integrated circuit with external programming capabilities is disclosed. A pin current source is provided for interfacing with at least one pin on the integrated circuit to control current flow there through to an external load interfaced to the at least one pin external to the integrated circuit. The external load has at least two discrete values. A voltage detector detects the voltage on the at least one pin and a state detector then compares the voltage on the at least one pin to at least two discrete voltage thresholds. Each of the discrete voltages is associated with a separate value of a control word, and the state detector is operable to determine the value of the control word associated with the detected voltage. The state detector then outputs the determined value of the control word.

公开(公告)号：US20060140034A1

公开(公告)日：2006-06-29

申请号：US11025778

申请日：2004-12-29

Applicant: Steven Hsu ,  Ram Krishnamurthy ,  Mark Anders

Inventor： Steven Hsu ,  Ram Krishnamurthy ,  Mark Anders

IPC: G11C7/00

CPC classification number: G11C7/08 ,  G11C7/065

Abstract: A sense amplifier includes a storage element and logic circuitry to transition encode an output signal.

Abstract translation: 读出放大器包括存储元件和用于转换对输出信号进行编码的逻辑电路。

公开(公告)号：US20060133183A1

公开(公告)日：2006-06-22

申请号：US11018012

申请日：2004-12-20

Applicant: Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

Inventor： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC: G11C8/00

CPC classification number: G11C11/413 ,  G11C7/12 ,  G11C11/56

Abstract: In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.

Abstract translation: 在一些实施例中，提供了包括位线和耦合到位线的位单元的电路。 位线有阻抗。 位单元在操作时都能够调整位线阻抗以指示存储的位值和至少两个读端口中选择的一个。 在此描述或以其他方式要求保护的其它实施例。

公开(公告)号：US06992603B2

公开(公告)日：2006-01-31

申请号：US10813084

申请日：2004-03-31

Applicant: Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I Ismail

Inventor： Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I Ismail

IPC: H03M7/00

CPC classification number: G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

Abstract translation: 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。

公开(公告)号：US06940313B2

公开(公告)日：2005-09-06

申请号：US09895278

申请日：2001-06-29

Applicant: Mark Anders ,  Ram Krishnamurthy

Inventor： Mark Anders ,  Ram Krishnamurthy

IPC: G06F13/40 ,  H01L27/108 ,  H03K19/0185 ,  H03K19/096

CPC classification number: G06F13/4077 ,  H03K19/01855 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.

Abstract translation: 在一个实施例中，动态总线包括具有约Vcc / 2的噪声容限的动态总线中继器。 总线中继器将总线分为前段和后段。 前段在后段评估时进行预充电，反之亦然。 动态总线中继器在后段被评估时隐藏从后段从前段传播的预充电信号。