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    Self-aligned buried strap process using doped HDP oxide
    31.
    发明授权
    Self-aligned buried strap process using doped HDP oxide 失效
    使用掺杂HDP氧化物的自对准掩埋工艺

    公开(公告)号：US06667504B1

    公开(公告)日：2003-12-23

    申请号：US10249228

    申请日：2003-03-24

    Applicant: Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    Inventor： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    IPC: H01L27108

    CPC classification number: H01L27/10867 ,  H01L27/10864 ,  H01L29/945

    Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

    Abstract translation: 本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电 埋在衬底中的邻近沟槽顶部氧化物的衬底。 沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

    High throughput chemical vapor deposition process capable of filling high aspect ratio structures
    32.
    发明授权
    High throughput chemical vapor deposition process capable of filling high aspect ratio structures 失效
    能够填充高纵横比结构的高通量化学气相沉积工艺

    公开(公告)号：US6030881A

    公开(公告)日：2000-02-29

    申请号：US72759

    申请日：1998-05-05

    Applicant: George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

    Inventor： George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

    IPC: C23C16/04 ,  C23C16/40 ,  C23C16/56 ,  H01L21/762

    CPC classification number: H01L21/76224 ,  C23C16/045 ,  C23C16/401 ,  C23C16/56

    Abstract: A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.

    Abstract translation: 提供了一种通过使用具有不同蚀刻速率 - 沉积速率（蚀刻/去除）比率的沉积和蚀刻步骤顺序的高密度等离子体（HDP）沉积工艺来填充高纵横比间隙而无空隙形成的方法。 第一步使用小于1的蚀刻/剥离比快速填充间隙。 第一步在打开间隙之前中断。 第二步使用大于1的蚀刻/剥离比来扩大间隙。 在形成间隙的元件的角部暴露之前停止第二步骤。 可以重复这些步骤，直到间隙的纵横比减小，使得无空隙间隙填充成为可能。 可以优化每个步骤的蚀刻/剥离比和持续时间，以实现高通量和高纵横比填充间隙。

    Apparatus for chemical vapor deposition of aluminum oxide
    33.
    发明授权
    Apparatus for chemical vapor deposition of aluminum oxide 失效
    氧化铝化学气相沉积装置

    公开(公告)号：US5614247A

    公开(公告)日：1997-03-25

    申请号：US316303

    申请日：1994-09-30

    Applicant: Steven G. Barbee ,  Richard A. Conti ,  Alexander Kostenko ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W. Wong ,  Steven P. Zuhoski

    Inventor： Steven G. Barbee ,  Richard A. Conti ,  Alexander Kostenko ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W. Wong ,  Steven P. Zuhoski

    IPC: C23C16/40 ,  C23C16/46 ,  C23C16/52 ,  H01L21/205 ,  H01L21/31

    CPC classification number: C23C16/403 ,  C23C16/46 ,  C23C16/52

    Abstract: An apparatus in a chemical vapor deposition (CVD) system monitors the actual wafer/substrate temperature during the deposition process. The apparatus makes possible the production of high quality aluminum oxide films with real-time wafer/substrate control. An infrared (IR) temperature monitoring device is used to control the actual wafer temperature to the process temperature setpoint. This eliminates all atmospheric temperature probing. The need for test runs and monitor waters as well as the resources required to perform the operations is eliminated and operating cost are reduced. High quality, uniform films of aluminum oxide can be deposited on a silicon substrates with no need for additional photolithographic steps to simulate conformality that are present in a sputtered (PVD) type application. The result is a reduction in required process steps with subsequent anticipated savings in equipment, cycle time, chemicals, reduce handling, and increased yield of devices on the substrate. The apparatus incorporates a heated source material, heated delivery lines, heated inert gas purge lines, a pressure differential mass flow controller, a control system with related valving, and a vacuum process chamber with walls that are temperature controlled as a complete source delivery system to accurately and repeatably provide source vapor for LPCVD deposition of aluminum oxide onto silicon substrates.

    Abstract translation: 化学气相沉积（CVD）系统中的装置在沉积过程中监测实际的晶片/衬底温度。 该设备使得可以生产具有实时晶片/衬底控制的高品质氧化铝膜。 使用红外（IR）温度监测装置将实际晶片温度控制到过程温度设定值。 这消除了所有的大气温度探测。 测试运行和监控水的需求以及执行操作所需的资源被消除，运行成本降低。 可以在硅衬底上沉积高质量均匀的氧化铝膜，而不需要额外的光刻步骤来模拟存在于溅射（PVD）型应用中的共形性。 结果是所需的工艺步骤减少，随后预期节省设备，循环时间，化学品，减少处理和提高基材上装置的产量。 该装置包括加热的源材料，加热的输送管线，加热的惰性气体吹扫管线，压差质量流量控制器，具有相关阀门的控制系统和具有作为完整源输送系统温度控制的壁的真空处理室 准确并重复地提供源蒸气，用于LPCVD在硅衬底上沉积氧化铝。

    Dual sidewall spacer for seam protection of a patterned structure
    34.
    发明授权
    Dual sidewall spacer for seam protection of a patterned structure 有权
    用于图案化结构的接缝保护的双侧壁间隔件

    公开(公告)号：US08664102B2

    公开(公告)日：2014-03-04

    申请号：US12751891

    申请日：2010-03-31

    Applicant: David L. O'Meara ,  Anthony Dip ,  Aelan Mosden ,  Pao-Hwa Chou ,  Richard A Conti

    Inventor： David L. O'Meara ,  Anthony Dip ,  Aelan Mosden ,  Pao-Hwa Chou ,  Richard A Conti

    IPC: H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.

    Abstract translation: 提供了具有双侧壁间隔件和成形方法的半导体器件。 该方法包括：在图案化结构上沉积第一间隔层，第一间隔层具有在衬底的表面的界面区附近传播穿过第一间隔层的厚度的接缝和图案化结构的侧壁，蚀刻 第一间隔层，以在界面区域处形成残留间隔物，其中残余间隔物涂覆小于图案化结构的侧壁的整体，在剩余间隔物上和在图案化结构的侧壁上沉积第二间隔层， 所述剩余间隔物，所述第二间隔层在所述残余间隔物的接缝上是无缝的，并且蚀刻所述第二间隔层以形成涂覆所述剩余间隔物并涂覆未被所述残留间隔物涂覆的所述图案化结构的侧壁的第二间隔物。

    MULTILAYER SIDEWALL SPACER FOR SEAM PROTECTION OF A PATTERNED STRUCTURE
    35.
    发明申请
    MULTILAYER SIDEWALL SPACER FOR SEAM PROTECTION OF A PATTERNED STRUCTURE 有权
    用于保护结构的多层平板隔墙

    公开(公告)号：US20110241128A1

    公开(公告)日：2011-10-06

    申请号：US12751926

    申请日：2010-03-31

    Applicant: David L. O'Meara ,  Anthony Dip ,  Aelan Mosden ,  Pao-Hwa Chou ,  Richard A. Conti

    Inventor： David L. O'Meara ,  Anthony Dip ,  Aelan Mosden ,  Pao-Hwa Chou ,  Richard A. Conti

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L21/28247 ,  H01L29/6656

    Abstract: A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.

    Abstract translation: 描述了具有多层侧壁间隔件和形成方法的半导体器件。 在一个实施例中，该方法包括在衬底的表面上提供含有图案化结构的衬底，并且在第一衬底温度下在第一衬底温度下沉积在图案化结构上的第一间隔层，其中第一间隔层包含第一材料。 该方法还包括在不同于第一衬底温度的第二衬底温度下在图案化衬底上沉积第二间隔层，其中第一和第二材料含有相同的化学元素，并且沉积步骤以任何顺序进行。 然后蚀刻第一和第二间隔层以在图案化结构上形成多层侧壁间隔物。

    Structure and method to control oxidation in high-k gate structures
    37.
    发明授权
    Structure and method to control oxidation in high-k gate structures 有权
    控制高k栅极结构氧化的结构和方法

    公开(公告)号：US07955926B2

    公开(公告)日：2011-06-07

    申请号：US12055682

    申请日：2008-03-26

    Applicant: Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

    Inventor： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

    IPC: H01L21/00

    CPC classification number: H01L21/76224 ,  H01L21/28123 ,  H01L29/517

    Abstract: In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

    Abstract translation: 在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。

    Mask forming and implanting methods using implant stopping layer and mask so formed
    38.
    发明授权
    Mask forming and implanting methods using implant stopping layer and mask so formed 失效
    使用植入物停止层和掩​​模形成的掩模形成和植入方法

    公开(公告)号：US07651947B2

    公开(公告)日：2010-01-26

    申请号：US11420321

    申请日：2006-05-25

    Applicant: Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

    Inventor： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

    IPC: H01L21/302

    CPC classification number: H01L21/266 ,  H01L21/26513 ,  Y10T428/24992

    Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

    Abstract translation: 形成用于植入衬底的掩模和使用具有光刻胶的注入阻挡层进行植入的方法提供了较低的纵横比掩模，其在去除掩模期间对衬底中的沟槽隔离造成最小的损害。 在一个实施例中，形成掩模的方法包括：在衬底上沉积注入阻挡层; 在所述注入阻挡层上沉积光致抗蚀剂，所述注入阻挡层的密度大于所述光致抗蚀剂; 通过去除光致抗蚀剂的一部分以暴露植入物停止层，在光致抗蚀剂中形成图案; 并通过蚀刻将图案转移到植入物停止层中以形成掩模。 注入停止层可以包括：氢化碳化锗，氮化碳化锗，氟化锗碳化物和/或无定形锗碳氢化物（GeHX），其中X包括碳。 方法/掩模减少了植入过程中的散射，因为掩模具有比常规掩模更高的密度。

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