公开(公告)号：US5528683A

公开(公告)日：1996-06-18

申请号：US425228

申请日：1995-04-17

Applicant: Luciano Tomasini ,  Rinaldo Castello

Inventor： Luciano Tomasini ,  Rinaldo Castello

IPC: H03F3/343 ,  H03F3/347 ,  H03H11/48 ,  H04B1/58 ,  H04M1/58 ,  H04M1/76 ,  H04M1/00

CPC classification number: H04M1/76 ,  H04B1/586 ,  H04M1/585

Abstract: The invention relates to a method and circuit for implementing an impedance associated with a monolithically integrated telephone subscriber circuit connected to a telephone line having a pair of terminals. The circuit consists of a resistor connected serially to one terminal of the telephone line, and a series of current mirror circuits. The current mirror circuits are connected in a closed loop configuration to the one terminal of the telephone line. The current mirror circuits divide, by a predetermined factor, the value of the resistor when a DC or very low frequency signal is input to the telephone circuit.

Abstract translation: 本发明涉及一种用于实现与连接到具有一对终端的电话线的单片电话用户电路相关联的阻抗的方法和电路。 该电路包括串联连接到电话线的一个端子的电阻器和一系列电流镜电路。 电流镜电路以闭环配置连接到电话线的一个终端。 电流镜电路将DC或极低频信号输入到电话电路时以预定的因数除以电阻的值。

公开(公告)号：US5136258A

公开(公告)日：1992-08-04

申请号：US768457

申请日：1991-09-30

Applicant: Germano Nicollini ,  Rinaldo Castello

Inventor： Germano Nicollini ,  Rinaldo Castello

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/45076 ,  H03F3/45183 ,  H03F2203/45026 ,  H03F2203/45036 ,  H03F2203/45192 ,  H03F2203/45251 ,  H03F2203/45288 ,  H03F2203/45318 ,  H03F2203/45658

Abstract: A circuit arrangement for enhancing the transconductance of a differential amplifier stage comprising a pair of MOS transistors, having respective source electrodes connected together through a circuit node, comprises a pair of active components respectively connected in each of the connections between the aforesaid electrodes and the aforesaid node and serving a characteristic function corresponding to that of a negative value resistor. This arrangement enables the transconductance of the differential stage to be increased while keeping the dissipated electric power low and the area occupied in an integrated circuit small.

Abstract translation: 一种用于增强包括一对MOS晶体管的差分放大器级的跨导的电路装置，其具有通过电路节点连接在一起的各个源极，包括分别连接在上述电极和上述电极之间的每个连接中的一对有源元件 并提供与负值电阻器相对应的特征函数。 这种布置使得能够增加差分级的跨导，同时保持耗散的功率低并且集成电路中占据的面积小。

公开(公告)号：US20120139764A1

公开(公告)日：2012-06-07

申请号：US13310587

申请日：2011-12-02

Applicant: Marco Sosio ,  Antonio Liscidini ,  Rinaldo Castello ,  Gabriele Gandolfi ,  Vittorio Colonna

Inventor： Marco Sosio ,  Antonio Liscidini ,  Rinaldo Castello ,  Gabriele Gandolfi ,  Vittorio Colonna

IPC: H03M3/02 ,  H03M1/36 ,  H03M1/12

CPC classification number: H03M1/06 ,  H03M3/344 ,  H03M3/368 ,  H03M3/424 ,  H03M3/454 ,  H03M3/456

Abstract: A filtering analog to digital converter (ADC) includes an integrator receiving at its input an analog input signal. A filtering capacitor at the input of the integrator filters out a large portion of out-of-band interferers in the analog input signal. The integrator produces an output that is quantized to produce a digital output. A feedback path between the quantizer output and the integrator input includes a digital to analog converter (DAC).

Abstract translation: 滤波模数转换器（ADC）包括积分器，在其输入端接收模拟输入信号。 积分器输入端的滤波电容滤除模拟输入信号中的大部分带外干扰源。 积分器产生一个被量化以产生数字输出的输出。 量化器输出和积分器输入之间的反馈路径包括数模转换器（DAC）。

公开(公告)号：US07880545B1

公开(公告)日：2011-02-01

申请号：US12397118

申请日：2009-03-03

Applicant: Alessandro Venca ,  Daniele Ottini ,  Francesco Rezzi ,  Rinaldo Castello

Inventor： Alessandro Venca ,  Daniele Ottini ,  Francesco Rezzi ,  Rinaldo Castello

IPC: H03F1/14

CPC classification number: H03F3/45475 ,  H03F1/14 ,  H03F1/34 ,  H03F3/3022 ,  H03F2200/153 ,  H03F2200/297

Abstract: The present invention provides compensation for circuits. In one embodiment, a compensation circuit has a first terminal coupled to an output terminal of the circuit and a second terminal coupled to feed back the output voltage to an internal node. A damping circuit may also be coupled to the output terminal. The damping circuit adds a pole and a zero to the transfer function of the circuit. In one embodiment, the damping circuit modifies the effect of the output impedance of a load on the transfer function to increase the phase margin of the circuit such that the circuit remains stable over an increased range of output capacitor values.

Abstract translation: 本发明提供对电路的补偿。 在一个实施例中，补偿电路具有耦合到电路的输出端的第一端子和耦合以将输出电压反馈到内部节点的第二端子。 阻尼电路也可以耦合到输出端子。 阻尼电路向电路的传递函数添加极点和零点。 在一个实施例中，阻尼电路改变负载的输出阻抗对传递函数的影响，以增加电路的相位裕度，使得电路在输出电容器值的增加范围内保持稳定。

公开(公告)号：US06411166B1

公开(公告)日：2002-06-25

申请号：US09864916

申请日：2001-05-23

Applicant: Andrea Baschirotto ,  Paolo Cusinato ,  Giampiero Montagna ,  Rinaldo Castello

Inventor： Andrea Baschirotto ,  Paolo Cusinato ,  Giampiero Montagna ,  Rinaldo Castello

IPC: H03F345

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

公开(公告)号：US06239653B1

公开(公告)日：2001-05-29

申请号：US08984107

申请日：1997-12-03

Applicant: Frencesco Rezzi ,  Rinaldo Castello ,  Marco Cazzaniga ,  Ivan Bietti

Inventor： Frencesco Rezzi ,  Rinaldo Castello ,  Marco Cazzaniga ,  Ivan Bietti

IPC: H03K500

CPC classification number: H03H11/0433

Abstract: The invention relates to an elementary biquadratic cell for programmable time-continuous analog filters. The biquadratic cell is coupled between a first voltage reference and a second voltage reference and has at least one pair of input terminals and first and second pairs of output terminals. The cell includes a pair of half-cells, which half-cells are structurally identical with each other. Each half-cell comprises at least a first transistor coupled between the first and the second voltage reference and having a base terminal connected to a respective one of the input terminals. Each half-cell further comprises second and third transistors coupled between the first and second voltage references. The second transistor has a base terminal connected to the first output terminal of the first pair of output terminals and a collector terminal connected to the first output terminal of the second pair of output terminals. The third transistor has a collector terminal connected to the first output terminal of the first pair of output terminals and a base terminal connected to the second output terminal of the second pair of output terminals.

Abstract translation: 本发明涉及用于可编程时间连续模拟滤波器的基本二次电池。 二次电池耦合在第一参考电压和第二参考电压之间，并且具有至少一对输入端和第一和第二对输出端。 细胞包括一对半细胞，半细胞在结构上彼此相同。 每个半电池包括耦合在第一和第二参考电压之间的至少第一晶体管，并且具有连接到相应输入端子的基极端子。 每个半电池还包括耦合在第一和第二电压基准之间的第二和第三晶体管。 第二晶体管具有连接到第一对输出端子的第一输出端子的基极端子和与第二对输出端子的第一输出端子连接的集电极端子。 第三晶体管具有连接到第一对输出端子的第一输出端子的集电极端子和连接到第二对输出端子的第二输出端子的基极端子。

公开(公告)号：US5825250A

公开(公告)日：1998-10-20

申请号：US757384

申请日：1996-11-27

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

IPC: H03F1/08 ,  H03F1/14

CPC classification number: H03F1/086

Abstract: An integrated operational amplifier with adjustable frequency compensation having a transconductance input stage and an amplifier output stage connected serially together between an input terminal and an output terminal of the operational amplifier. For the purpose of frequency compensation, moreover, a compensation block is connected across the input and the output of the output stage. The compensation block uses a plurality of charge storage elements connected in parallel together and in series with switch block which selects a sub-plurality of said charge storage elements in response to an external signal of the amplifier. The compensation block thereby provides an overall effective capacitance for frequency compensation.

Abstract translation: 具有可变频率补偿的集成运算放大器，具有串联连接在运算放大器的输入端和输出端之间的跨导输入级和放大器输出级。 此外，为了频率补偿的目的，在输出级的输入端和输出端之间连接补偿块。 补偿块使用并联连接并与开关块串联的多个电荷存储元件，该开关块响应于放大器的外部信号选择子多个所述电荷存储元件。 因此，补偿块为频率补偿提供总体有效电容。

公开(公告)号：US5815037A

公开(公告)日：1998-09-29

申请号：US651106

申请日：1996-05-21

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Ivan Bietti ,  Giancarlo Clerici

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Ivan Bietti ,  Giancarlo Clerici

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45982 ,  H03F2203/45526

Abstract: A high-pass filter includes at least one circuit unit constituted by a first branch and a second branch both connected to an input of the filter on one side and, on the other side, to an adder the output of which is the output of the filter. The first branch includes means for transferring an input signal substantially without modifying its frequency content, and the second branch comprises a low-pass filter. The circuit elements are chosen such that the components of the input signal with frequencies below the cut-off frequency of the low-pass filter are substantially cancelled out at the output of the adder. The filter is suitable for being produced within a particularly small area in an integrated circuit.

Abstract translation: 高通滤波器包括由一侧连接到滤波器的输入的第一分支和第二分支构成的至少一个电路单元，另一侧由加法器输出，该加法器的输出为 过滤。 第一分支包括用于基本上不修改其频率内容来传送输入信号的装置，并且第二分支包括低通滤波器。 电路元件被选择为使得低于低通滤波器的截止频率的输入信号的分量在加法器的输出处基本抵消。 该滤波器适合于在集成电路的特别小的区域内产生。

公开(公告)号：US5587682A

公开(公告)日：1996-12-24

申请号：US413772

申请日：1995-03-30

Applicant: Gianluca Colli ,  Massimo Franciotta ,  Rinaldo Castello

Inventor： Gianluca Colli ,  Massimo Franciotta ,  Rinaldo Castello

IPC: G06G7/163 ,  G06G7/16 ,  H03K5/22

CPC classification number: G06G7/163

Abstract: An analog multiplier circuit includes three transconductance stages. One of the transconductance stages, receiving a first differential voltage, conducts a differential current responsive to the first differential voltage from the other two transconductance stages. The differential current changes the transconductance in the other two transconductance stages, which are cross-coupled with one another. The second differential input voltage is presented to the other two transconductance stages in parallel, resulting in an output differential current or voltage based on the product of the first and second differential input voltages. Each of the transconductance stages is implemented in BiCMOS, and each includes two differential legs, each having a MOS transistor receiving an input signal and a cascode bipolar transistor. Each transconductance stage also includes a reference leg which develops the drain-source voltage for the MOS transistors; the first transconductance stage differentially varies this drain-source voltage in the other two stages to produce the product.

Abstract translation: 模拟乘法器电路包括三个跨导级。 接收第一差分电压的跨导级中的一个传导响应于来自其它两个跨导级的第一差分电压的差分电流。 差分电流改变了另外两个跨导级的跨导，它们彼此交叉耦合。 第二差分输入电压并联提供给另外两个跨导级，导致基于第一和第二差分输入电压的乘积的输出差分电流或电压。 每个跨导级在BiCMOS中实现，并且每个跨导级包括两个差分支路，每个支路具有接收输入信号的MOS晶体管和共源共栅双极晶体管。 每个跨导级还包括产生MOS晶体管的漏 - 源电压的参考支路; 第一跨导级在其他两个阶段差异地改变该漏极 - 源极电压以产生该产品。

公开(公告)号：US5576646A

公开(公告)日：1996-11-19

申请号：US473533

申请日：1995-06-07

Applicant: Francesco Rezzi ,  Andrea Baschirotto ,  Rinaldo Castello

Inventor： Francesco Rezzi ,  Andrea Baschirotto ,  Rinaldo Castello

IPC: H03F3/34 ,  H03F3/45 ,  H03H11/04 ,  H03K5/22 ,  H03K17/60

CPC classification number: H03F3/45076 ,  H03H11/0433 ,  H03F2200/261

Abstract: The invention relates to a transconductor circuit with a double input and a single output, comprising two input transistors (M1, M2) whose primary conduction terminals (D1, S1, D2, S2) are respectively connected together; in this way, variations in load current and voltage can be made lower, thereby also lowering distortion from changes in their transconductance.

Abstract translation: 本发明涉及具有双输入和单输出的跨导电路，包括其一次导通端子（D1，S1，D2，S2）分别连接在一起的两个输入晶体管（M1，M2） 以这种方式，可以降低负载电流和电压的变化，从而也降低其跨导变化的变形。