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公开(公告)号：US07880545B1
公开(公告)日：2011-02-01
申请号：US12397118
申请日：2009-03-03
IPC分类号： H03F1/14
CPC分类号： H03F3/45475 , H03F1/14 , H03F1/34 , H03F3/3022 , H03F2200/153 , H03F2200/297
摘要： The present invention provides compensation for circuits. In one embodiment, a compensation circuit has a first terminal coupled to an output terminal of the circuit and a second terminal coupled to feed back the output voltage to an internal node. A damping circuit may also be coupled to the output terminal. The damping circuit adds a pole and a zero to the transfer function of the circuit. In one embodiment, the damping circuit modifies the effect of the output impedance of a load on the transfer function to increase the phase margin of the circuit such that the circuit remains stable over an increased range of output capacitor values.
摘要翻译： 本发明提供对电路的补偿。 在一个实施例中，补偿电路具有耦合到电路的输出端的第一端子和耦合以将输出电压反馈到内部节点的第二端子。 阻尼电路也可以耦合到输出端子。 阻尼电路向电路的传递函数添加极点和零点。 在一个实施例中，阻尼电路改变负载的输出阻抗对传递函数的影响，以增加电路的相位裕度，使得电路在输出电容器值的增加范围内保持稳定。
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公开(公告)号：US06654192B1
公开(公告)日：2003-11-25
申请号：US09294642
申请日：1999-04-19
IPC分类号： G11B509
CPC分类号： G01R19/22
摘要： A full-wave rectifier for monitoring the amplitude of a differential analog signal includes a differential Track&Hold stage controlled by a first differential logic timing signal tracking the differential analog input signal during a tracking phase that corresponds to a high logic stage of the first differential timing signal. This produces a differential output signal that is a replica of the input signal and the signal is stored during a successive storing phase that corresponds to a low logic state of the first differential timing signal. A first differential output amplifier includes inputs coupled to the output of the Track&Hold stage. A differential bistable circuit, controlled by a second differential logic timing signal, includes inputs coupled to the differential outputs of the first amplifier and produces a third differential logic control signal. A second multiplexed amplifier, controlled by the third differential control signal, includes inputs coupled to the output of the Track&Hold stage and produces a differential analog signal having an amplitude function corresponding to the amplitude of the differential input signal. A timing circuit receives at an input a differential logic synchronizing signal and generates the first differential timing signal of the Track&Hold stage and the second differential timing signal of the bistable circuit.
摘要翻译： 用于监视差分模拟信号的幅度的全波整流器包括差分跟踪和保持级，该差分跟踪保持级由跟踪第一差分定时信号的高逻辑级的跟踪阶段期间的差分模拟输入信号的第一差分逻辑定时信号控制 。 这产生作为输入信号的副本的差分输出信号，并且在对应于第一差分定时信号的低逻辑状态的连续存储阶段期间存储信号。 第一差分输出放大器包括耦合到跟踪和保持级的输出的输入。 由第二差分逻辑定时信号控制的差分双稳态电路包括耦合到第一放大器的差分输出并输出第三差分逻辑控制信号的输入。 由第三差分控制信号控制的第二多路复用放大器包括耦合到跟踪和保持级的输出的输入，并且产生具有对应于差分输入信号的幅度的幅度函数的差分模拟信号。 定时电路在输入端接收差分逻辑同步信号，并产生跟踪和保持级的第一差分定时信号和双稳态电路的第二差分定时信号。
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3.发明授权Time interleaved digital signal processing in a read channel with reduced noise configuration 有权在具有降低的噪声配置的读通道中的时间交错数字信号处理公开(公告)号：US06496550B1
公开(公告)日：2002-12-17
申请号：US09444340
申请日：1999-11-19
IPC分类号： H04L2708
CPC分类号： G11B20/10277 , G11B20/10509
摘要： A read and analog-to-digital data conversion channel includes an input circuit receiving an input data stream, and a time interleaved analog-to-digital converter connected to the input circuit. The time interleaved analog-to-digital converter includes a pair of analog-to-digital converters functioning in parallel and at half the clock frequency. A signal path through the time interleaved analog-to-digital converter is subdivided into two parallel paths through the pair of analog-to-digital converters. There is a first path for even bits and a second path for odd bits. A digital post-processing circuit is connected to the two parallel paths of the time interleaved analog-to-digital converter, and has an output providing a reconstructed data stream. At least one adjusting digital-to-analog converter is connected between the digital post-processing circuit and the input circuit for control thereof. The conversion channel further includes an offset circuit for compensating an offset in the pair of analog-to-digital converters in the time interleaved analog-to-digital converter. The offset circuit is controlled by the digital post-processing circuit, and includes first and second distinct offset compensating circuits independently controlled by the digital post-processing circuit.
摘要翻译： 读取和模数转换数据转换通道包括接收输入数据流的输入电路和连接到输入电路的时间交错模数转换器。 时间交织的模数转换器包括并行和半个时钟频率工作的一对模 - 数转换器。 通过时间交织的模数转换器的信号路径被分成通过该对模数转换器的两条并行路径。 有一个偶数位的第一个路径，奇数位的第二个路径。 数字后处理电路连接到时间交错模数转换器的两个并行路径，并且具有提供重构数据流的输出。 至少一个调节数模转换器连接在数字后处理电路和输入电路之间，用于控制。 转换通道还包括用于补偿时间交织模数转换器中的该对模数转换器中的偏移的偏移电路。 偏移电路由数字后处理电路控制，并且包括由数字后处理电路独立控制的第一和第二不同偏移补偿电路。
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公开(公告)号：US06362681B1
公开(公告)日：2002-03-26
申请号：US09461782
申请日：1999-12-15
IPC分类号： H03K500
CPC分类号： H03H11/0422
摘要： A low pass filter with programmable equalization includes at least one biquadratic cell and a converter of the input voltage into a current, proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell to introduce two real and opposed zeros in the transfer function of the filter. The low pass filter includes two structurally similar circuits functionally connected in cascade. Each circuit includes a biquadratic cell and an input stage having two outputs injecting, through a first current output, the current to an input capacitor of the respective biquadratic cell, by a direct coupling in a first of the two circuits and in an inverted manner in the second of the two circuits. A second voltage output is coupled to an input of the respective biquadratic cell.
摘要翻译： 具有可编程均衡的低通滤波器包括至少一个二次电池和将输入电压转换为与输入电压的导数成比例的电流的转换器，其被注入到二次电池的节点上以引入两个实际和相对的零 在滤波器的传递函数中。 低通滤波器包括在功能上串联连接的两个结构相似的电路。 每个电路包括一个二次电池单元和一个具有两个输出端的输入级，输出端通过第一电流输出将电流通过两个电路中的第一个电路中的直接耦合并以相反的方式在相应的二次电池单元的输入电容器中注入 这两个电路中的第二个。 第二电压输出耦合到相应的双二次电池的输入端。
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公开(公告)号：US06466097B1
公开(公告)日：2002-10-15
申请号：US09421643
申请日：1999-10-20
IPC分类号： H03L706
CPC分类号： H03L7/0893 , H03L7/0896
摘要： A phase locked loop is provided that includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator. The charge pump circuit includes two symmetric branches, feedback paths, and circuit breaking switches. Each of the symmetric branches has a constant current generator and a pulsed current generator, with one terminal of the loop filter being connected to one of the symmetric branches and the other terminal of the loop filter being connected to the other of the symmetric branches. The feedback paths control the constant current generators based on voltages at the terminals of the loop filter, and each of the circuit breaking switches couple one of the pulsed current generators and the corresponding terminal of the loop filter. The pulsed current generators supply a first current whose amplitude is proportional to an amplitude of a second current supplied by the constant current generators through the duty cycle of the first current. In a preferred embodiment, the circuit breaking switches are controlled by phase error signals from the phase comparator. A method for controlling a charge pump circuit in a phase locked loop is also provided.
摘要翻译： 提供了一个锁相环，其包括相位比较器，电荷泵电路，环路滤波器和压控振荡器。 电荷泵电路包括两个对称分支，反馈路径和断路开关。 每个对称分支具有恒定电流发生器和脉冲电流发生器，环路滤波器的一个端子连接到一个对称分支，并且环路滤波器的另一个端子连接到另一个对称分支。 反馈路径基于环路滤波器的端子处的电压来控制恒定电流发生器，并且每个断路开关耦合脉冲电流发生器中的一个和环路滤波器的相应端子。 脉冲电流发生器通过第一电流的占空比来提供其振幅与由恒定电流发生器提供的第二电流的振幅成比例的第一电流。 在优选实施例中，断路开关由来自相位比较器的相位误差信号控制。 还提供了一种用于控制锁相环中的电荷泵电路的方法。
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6.发明授权Analog-to-digital flash converter for generating a thermometric digital code 有权用于产生温度数字代码的模拟 - 数字闪存转换器公开(公告)号：US06346905B1
公开(公告)日：2002-02-12
申请号：US09447065
申请日：1999-11-22
IPC分类号： H03M1300
CPC分类号： H03M1/0809 , H03M1/365
摘要： A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.
摘要翻译： 闪存模数转换器包括具有差分输出的一组比较器，产生测温代码和一组三输入逻辑或非门。 通过提供包括多个分压器的无源接口，每个连接在相应比较器的非反相输出端和该组的较高阶比较器的反相输出端之间，该转换器具有增强的抗噪声能力和减小的不精确性。 该组的对应逻辑或非门具有耦合到相应比较器的反相输出的第一输入，耦合到高阶比较器的非反相输出的第二输入和耦合到分压器的中间节点的第三输入。
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公开(公告)号：US06215436B1
公开(公告)日：2001-04-10
申请号：US09296985
申请日：1999-04-22
IPC分类号： H03M136
摘要： A differential decoder has a wide output dynamic range and reduced area consumption. The decoder includes a plurality of inputs which are correlated to a plurality of output lines. The output lines are driven by respective NPN type bipolar transistors which are connected to the output lines by their emitters while the input signals are fed to their bases. The decoder also includes a plurality of additional output lines which are complementary to the output lines and another plurality of NPN type bipolar transistors which are suitable to drive the additional output lines. The additional bipolar transistors are connected to the additional output lines through their emitter terminals, and are connected to the base and collector terminals of the bipolar transistors that drive the output lines, through their base and collector terminals.
摘要翻译： 差分解码器具有宽的输出动态范围和减少的面积消耗。 解码器包括与多条输出线相关联的多个输入。 输出线由相应的NPN型双极晶体管驱动，它们通过其发射极连接到输出线，同时将输入信号馈送到它们的基极。 解码器还包括与输出线互补的多个附加输出线和适于驱动附加输出线的另外多个NPN型双极晶体管。 附加的双极晶体管通过其发射极端子连接到附加输出线，并且通过其基极和集电极端子连接到驱动输出线的双极晶体管的基极和集电极端子。
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