公开(公告)号：US08314024B2

公开(公告)日：2012-11-20

申请号：US12454322

申请日：2009-05-15

Applicant: Darrell Rinerson ,  Robin Cheung

Inventor： Darrell Rinerson ,  Robin Cheung

IPC: H01L21/768

CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

公开(公告)号：US20120012897A1

公开(公告)日：2012-01-19

申请号：US13185410

申请日：2011-07-18

Applicant: PAUL BESSER ,  ROBIN CHEUNG ,  WEN ZHONG KONG

Inventor： PAUL BESSER ,  ROBIN CHEUNG ,  WEN ZHONG KONG

IPC: H01L23/52

CPC classification number: H01L27/101 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

Abstract: A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required.

Abstract translation: 使用在前端（FEOL）衬底上形成的后端（BEOL）形成的沟槽阵列形成的非闪存非易失性交叉沟槽存储器阵列包括两端 存储元件可操作地存储形成在第一沟槽和第二沟槽的交叉点处的至少一个数据位。 第一和第二沟槽彼此正交配置。 至少一层存储器包括多个第一和第二沟槽以形成多个存储元件。 非易失性存储器可用于替换或模拟其它存储器类型，包括但不限于嵌入式存储器，DRAM，SRAM，ROM和FLASH。 存储器可以随机寻址到位电平，并且不需要在写操作之前擦除或擦除擦除操作。

公开(公告)号：US07897951B2

公开(公告)日：2011-03-01

申请号：US11881496

申请日：2007-07-26

Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

IPC: H01L29/02 ,  H01L29/06

CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

公开(公告)号：US20100265762A1

公开(公告)日：2010-10-21

申请号：US12803214

申请日：2010-06-21

Applicant: Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hasen

Inventor： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hasen

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165 ,  Y10S257/903

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include anon-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电连接的欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

公开(公告)号：US20100159641A1

公开(公告)日：2010-06-24

申请号：US12653851

申请日：2009-12-18

Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  David Hansen ,  Robin Cheung ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  David Hansen ,  Robin Cheung ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

IPC: H01L21/34

CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

公开(公告)号：US20090026442A1

公开(公告)日：2009-01-29

申请号：US11881496

申请日：2007-07-26

Applicant: Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

Inventor： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

IPC: H01L29/15

CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

公开(公告)号：US20090026441A1

公开(公告)日：2009-01-29

申请号：US11881474

申请日：2007-07-26

Applicant: Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

Inventor： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

IPC: H01L29/15

CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165 ,  Y10S257/903

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

公开(公告)号：US07393795B2

公开(公告)日：2008-07-01

申请号：US11346400

申请日：2006-02-01

Applicant: Robin Cheung ,  Siyi Li

Inventor： Robin Cheung ,  Siyi Li

IPC: H01L21/302

CPC classification number: H01L21/3105 ,  H01L21/31116 ,  H01L21/31138

Abstract: Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.

Abstract translation: 在本发明中提供了在电介质膜上进行蚀刻后沉积的方法。 在一个实施例中，该方法包括提供在蚀刻反应器中设置在其上的低k电介质层的衬底，蚀刻蚀刻反应器中的低k电介质层，以及在蚀刻的低k电介质层上形成保护层。 在另一个实施例中，该方法包括提供在蚀刻反应器中设置在其上的低k电介质层的衬底，蚀刻反应器中的低k电介质层，将蚀刻的低k电介质层与供应到 反应器，在蚀刻的低k电介质层上形成保护层，以及去除蚀刻的低k电介质层上形成的保护层。

公开(公告)号：US20070175858A1

公开(公告)日：2007-08-02

申请号：US11346400

申请日：2006-02-01

Applicant: Robin Cheung ,  Siyi Li

Inventor： Robin Cheung ,  Siyi Li

IPC: B44C1/22 ,  B05D3/00 ,  B05D3/10

CPC classification number: H01L21/3105 ,  H01L21/31116 ,  H01L21/31138

Abstract: Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.

Abstract translation: 在本发明中提供了在电介质膜上进行蚀刻后沉积的方法。 在一个实施例中，该方法包括提供在蚀刻反应器中设置在其上的低k电介质层的衬底，蚀刻蚀刻反应器中的低k电介质层，以及在蚀刻的低k电介质层上形成保护层。 在另一个实施例中，该方法包括提供在蚀刻反应器中设置在其上的低k电介质层的衬底，蚀刻反应器中的低k电介质层，将蚀刻的低k电介质层与供应到 反应器，在蚀刻的低k电介质层上形成保护层，以及去除蚀刻的低k电介质层上形成的保护层。

公开(公告)号：US06929774B2

公开(公告)日：2005-08-16

申请号：US10701387

申请日：2003-11-04

Applicant: Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

Inventor： Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

IPC: H01L21/31 ,  H01L21/00 ,  H01L21/324 ,  H01L21/677 ,  F26B7/00

CPC classification number: H01L21/67109 ,  H01L21/67115 ,  H01L21/67748

Abstract: A method and apparatus for heating and cooling a substrate are provided. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism.

Abstract translation: 提供了一种用于加热和冷却衬底的方法和装置。 提供了一种室，其包括适于加热位于加热机构附近的基板的加热机构，与加热机构间隔开并适于冷却位于冷却机构附近的基板的冷却机构，以及适于将基板 靠近加热机构的位置和靠近冷却机构的位置。