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31.发明公开公开(公告)号：US20240144499A1
公开(公告)日：2024-05-02
申请号：US18543856
申请日：2023-12-18
Applicant: Socionext Inc.
Inventor： Kazuyuki OHHASHI
CPC classification number: G06T7/33 , G06T3/00 , G06T7/20 , G06T7/579 , G06T7/74 , G06T2207/10028 , G06T2207/20212 , G06T2207/30244 , G06T2207/30252
Abstract: An information processing device includes a VSLAM processing unit as an acquisition unit, a difference calculation unit and an offset processing unit as alignment processing units, and an integration unit as an integration processing unit. The VSLAM processing unit acquires first point cloud information based on first image data obtained from a first image capturing unit provided at a first position of a moving body, and acquires second point cloud information based on second image data obtained from a second image capturing unit provided at a second position different from the first position of the moving body. The difference calculation unit and offset processing unit perform alignment processing on the first and second point cloud information. The integration unit generates integrated point cloud information by using the first point cloud information and the second point cloud information on both of which the alignment processing has been performed.
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公开(公告)号：US11967593B2
公开(公告)日：2024-04-23
申请号：US17529252
申请日：2021-11-17
Applicant: SOCIONEXT INC.
Inventor： Kazuya Okubo
IPC: H01L27/02 , H01L23/528 , H01L23/60
CPC classification number: H01L27/0292 , H01L23/5286 , H01L23/60
Abstract: A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate.
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公开(公告)号：US20240112746A1
公开(公告)日：2024-04-04
申请号：US18538722
申请日：2023-12-13
Applicant: SOCIONEXT INC.
Inventor： Yasumitsu SAKAI , Shinichi MORIWAKI
IPC: G11C17/12 , G11C5/06 , G11C11/4074 , G11C11/408 , G11C11/4094
CPC classification number: G11C17/12 , G11C5/063 , G11C11/4074 , G11C11/4085 , G11C11/4094
Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.
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公开(公告)号：US20240073390A1
公开(公告)日：2024-02-29
申请号：US18453767
申请日：2023-08-22
Applicant: Socionext Inc.
Inventor： Yuji UMEZU , Soichi HAGIWARA
CPC classification number: H04N9/78 , H04N23/815 , H04N23/843
Abstract: An image processing device includes a memory and a processor configured to separate first image data obtained by an image sensor having a Bayer arrangement, into second image data that includes brightness information, and third image data that includes color information and has a lower resolution than the first image data and the second image data, wherein a pixel arrangement of the third image data includes two pixels in each of a horizontal direction and a vertical direction, among which two pixels on one diagonal are of a same type, two pixels on another diagonal are of types different from each other, and the two pixels on said another diagonal are of the types different from the two pixels on the one diagonal.
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公开(公告)号：US11916057B2
公开(公告)日：2024-02-27
申请号：US17245509
申请日：2021-04-30
Applicant: SOCIONEXT INC.
Inventor： Yoko Shiraki
IPC: H01L23/00 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/092 , H01L29/00 , H01L29/06 , H01L29/775
CPC classification number: H01L27/0207 , H01L23/5286 , H01L27/092 , H01L29/0673 , H01L29/775
Abstract: A layout structure of a standard cell using a complementary FET (CFET) is provided. The standard cell includes a first three-dimensional transistor and a second three-dimensional transistor formed above the first transistor in the depth direction, between buried first and second power supply lines. A first contact connects a local interconnect connected to the first transistor and the first power supply line. A second contact connects a local interconnect connected to the second transistor and the second power supply line. The second contact is longer in the depth direction and greater in size in planar view than the first contact.
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Patent Agency Ranking
公开(公告)号：US11908799B2
公开(公告)日：2024-02-20
申请号：US17322570
申请日：2021-05-17
Applicant: SOCIONEXT INC.
Inventor： Hideyuki Komuro , Junji Iwahori
IPC: H01L23/528 , H01L23/535 , H01L27/092
CPC classification number: H01L23/5286 , H01L23/535 , H01L27/092
Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.
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公开(公告)号：US11882269B2
公开(公告)日：2024-01-23
申请号：US17231470
申请日：2021-04-15
Applicant: SOCIONEXT INC.
Inventor： Yuya Shigenobu , Masao Kitagawa
IPC: H04N19/103
CPC classification number: H04N19/103
Abstract: An image encoding method includes, using an image as input, determining a first mode suited to encode the image in accordance with a first processing procedure; using the image as input, determining a second mode suited to encode the image in accordance with a second processing procedure; selecting one of first mode and the second mode as a final mode; encoding the image, using the final mode; and calculating a cost of using the second mode to encode the image. The second processing procedure is implemented by a reconfigurable circuit. In the selecting, the first mode is selected when the cost calculated in the calculating is higher than a first predetermined value, and the second mode is selected when the cost is lower than or equal to the first predetermined value.
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公开(公告)号：US20240021735A1
公开(公告)日：2024-01-18
申请号：US18358689
申请日：2023-07-25
Applicant: SOCIONEXT INC.
Inventor： Hiroyuki SHIMBO
IPC: H01L29/786 , H01L21/8238 , H01L27/092 , H01L27/118 , H01L29/06 , H01L29/775 , H01L27/088 , H01L29/417 , H01L29/423
CPC classification number: H01L29/78696 , H01L21/8238 , H01L27/092 , H01L27/11807 , H01L29/06 , H01L29/775 , H01L27/088 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L21/823412
Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire PET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.
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公开(公告)号：US11863199B2
公开(公告)日：2024-01-02
申请号：US17959887
申请日：2022-10-04
Applicant: Socionext Inc.
Inventor： Saul Darzy
Abstract: Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.
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公开(公告)号：US11846720B2
公开(公告)日：2023-12-19
申请号：US17119639
申请日：2020-12-11
Applicant: SOCIONEXT INC.
Inventor： Joji Hayashi
Abstract: A divider control circuit outputs a divider control signal that is meant to increase the division ratio from a first division ratio through a second division ratio greater than the first division ratio to a third division ratio greater than the second division ratio and then return the division ratio through a fourth division ratio smaller than the third division ratio to a fifth division ratio smaller than the fourth division ratio and greater than the first division ratio. Moreover, control is exerted so that the absolute value of the time rate of change of the division ratio in the increase from the second division ratio to the third division ratio is smaller than the absolute value of the time rate of change of the division ratio in the increase from the first division ratio to the second division ratio.
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