公开(公告)号：US20030173588A1

公开(公告)日：2003-09-18

申请号：US10339640

申请日：2003-01-09

Applicant: STMICROELECTRONICS S.A.

Inventor： Raul Andres Bianchi

IPC: H01L031/072

CPC classification number: G06F17/5036

Abstract: A system is provided for modeling an integrated circuit including at least one insulated-gate field-effect transistor. The system includes generator means for defining a parameter representing mechanical stresses applied to the active area of the transistor, and processing means for determining at least one of the electrical parameters of the transistor based at least partially on the stress parameter. Also provided is a method of modeling an integrated circuit including at least one insulated-gate field-effect transistor, and a method of producing an integrated circuit including at least one insulated-gate field-effect transistor.

公开(公告)号：US20030155611A1

公开(公告)日：2003-08-21

申请号：US10378198

申请日：2003-03-03

Applicant: STMicroelectronics S.A.

Inventor： Alain Chantre ,  Michel Marty ,  Helene Baudry

IPC: H01L029/76

CPC classification number: H01L29/66242 ,  H01L29/66272

Abstract: The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.

Abstract translation: 该制造工艺包括产生具有非本征基极和本征基极的基极区域的相位，以及产生发射极区域的相位，该发射极区域包括位于位于本征基底之上的发射极窗口中的较窄的下部的发射极阵列。 外在基底的制造包括在发射器窗口被限定之后进行的掺杂剂的注入，在距离发射器窗口的横向边界的任一侧和预定距离dp处，以便相对于该发射极自对准 窗口，并且在发射极块形成之前。

公开(公告)号：US20030133344A1

公开(公告)日：2003-07-17

申请号：US10352581

申请日：2003-01-28

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: G11C007/00

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

公开(公告)号：US20030132796A1

公开(公告)日：2003-07-17

申请号：US10303650

申请日：2002-11-25

Applicant: STMicroelectronics S.A.

Inventor： Bruno Gailhard ,  Olivier Ferrand

IPC: G05F001/10

CPC classification number: G05F3/30 ,  G05F3/267

Abstract: A temperature-compensated current source includes a first arm fixing a reference voltage, a second arm fixing a reference current, and a third arm providing an output current obtained by copying the reference current in a first current mirror. A second current mirror copies, in the voltage reference arm, the reference current while a voltage copying circuit copies the reference voltage at a node of the second arm connected to ground by a first resistor series-connected with n parallel-connected diodes. A second resistor is parallel-connected with the assembly formed by the first resistor series-connected with the n parallel-connected diodes.

Abstract translation: 温度补偿电流源包括固定参考电压的第一臂，固定参考电流的第二臂和提供通过在第一电流镜中复制参考电流而获得的输出电流的第三臂。 第二电流镜在电压参考臂中复制参考电流，而电压复制电路通过与n个并联连接的二极管串联连接的第一电阻器连接到地的第二臂的节点复制参考电压。 第二电阻器与由与n个并联二极管串联连接的第一电阻器形成的组件并联连接。

公开(公告)号：US20030129812A1

公开(公告)日：2003-07-10

申请号：US10346444

申请日：2003-01-17

Applicant: STMicroelectronics S.A.

Inventor： Gerard Auriel ,  Laurent Cornibert

IPC: H01L021/22

CPC classification number: H01L29/74 ,  H01L21/2257 ,  H01L21/761 ,  H01L21/763 ,  H01L29/0619 ,  H01L29/66333 ,  H01L29/66393

Abstract: A method for manufacturing a vertical power component on a silicon wafer, including the steps of growing a lightly-doped epitaxial layer of a second conductivity type on the upper surface of a heavily-doped substrate of a first conductivity type, the epitaxial layer having a thickness adapted to withstanding the maximum voltage likely to be applied to the power component during its operation; and delimiting in the wafer an area corresponding to at least one power component by an isolating wall formed by etching a trench through the epitaxial layer and diffusing from this trench a dopant of the first conductivity type of high doping level.

公开(公告)号：US20030123362A1

公开(公告)日：2003-07-03

申请号：US10320757

申请日：2002-12-16

Applicant: STMicroelectronics S.A.

Inventor： Philippe Graffouliere

IPC: G11B007/00

CPC classification number: G11B20/10009 ,  G11B20/1426 ,  G11B20/18

Abstract: A symbol length is evaluated on the basis of receiving a first-symbol length, and a phase error with respect to detection of a length of the first symbol before receiving a length of a second symbol following the first symbol. The process includes evaluating at least two random phase errors on the basis of the phase error received. A first random phase error is dependent on a deterministic phase error with respect to a first state corresponding to an absence of a corrected first-symbol length. A second random phase error is dependent on a deterministic phase error with respect to a second state corresponding to the corrected first-symbol length. The process includes retaining as an evaluated symbol length the first-symbol length received if the absolute value of the first random phase error reduces a condition of passing through the first state. The second step also retains as an evaluated symbol length the corrected first-symbol length if the absolute value of the second random phase error reduces the condition of passing through the second state.

Abstract translation: 基于接收第一符号长度和相对于在接收第一符号之后的第二符号的长度的第一符号的长度的检测的相位误差来评估符号长度。 该过程包括基于接收到的相位误差来评估至少两个随机相位误差。 第一随机相位误差取决于相对于不存在校正的第一符号长度的第一状态的确定性相位误差。 第二随机相位误差取决于对应于校正的第一符号长度的第二状态的确定性相位误差。 该过程包括如果第一随机相位误差的绝对值减少通过第一状态的条件，则保留作为评估符号长度接收的第一符号长度。 如果第二随机相位误差的绝对值降低了通过第二状态的条件，则第二步骤还将经评估的符号长度保留为校正的第一符号长度。

公开(公告)号：US20030122531A1

公开(公告)日：2003-07-03

申请号：US10237164

申请日：2002-09-06

Applicant: STMicroelectronics S.A.

Inventor： Jerome Nebon ,  Alexandre Balmefrezol

IPC: G05F001/40

CPC classification number: H02M3/156

Abstract: A switched mode power supply device comprising a power transistor periodically set to conduction and supplying a regulated voltage that comprises a ramp generation circuit controlled by a clock signal and periodically generating a ramp voltage. The device includes an amplifier error circuit between a reference voltage and said regulated output voltage and generates an error signal, and a comparator comparing the ramp voltage with said error voltage and providing an output signal for controlling said power circuit. The circuit is characterized in that it comprises a delay element delaying the setting to conduction of the power transistor so as to desynchronize the starting of the ramp and said setting to conduction.

Abstract translation: 一种开关模式电源装置，包括周期性地设置为导通的功率晶体管并且提供包括由时钟信号控制的斜坡发生电路并周期性地产生斜坡电压的稳压电压。 该装置包括参考电压和所述调节输出电压之间的放大器误差电路，并产生误差信号，以及将斜坡电压与所述误差电压进行比较并提供用于控制所述电源电路的输出信号的比较器。 该电路的特征在于它包括延迟元件延迟功率晶体管导通的设置，以使斜坡的起始和所述设置的导通失速。

公开(公告)号：US20030118079A1

公开(公告)日：2003-06-26

申请号：US10325491

申请日：2002-12-19

Applicant: STMicroelectronics S.A.

Inventor： Fabrice Marinet ,  Benjamin Duval

IPC: G01K007/00

CPC classification number: G01K3/005 ,  G01K15/00

Abstract: An integrated temperature sensor delivers threshold detection signals when temperature thresholds have been exceeded. The temperature sensor includes a circuit for detecting a first temperature threshold having a first detection threshold, and for detecting a second temperature threshold having a second detection threshold. The circuit also detects a third temperature threshold between the first and second temperature thresholds, and detects a fourth temperature threshold between the first and second temperature thresholds. The third temperature threshold has a third detection threshold linked with the first detection threshold so that a deviation of the first detection threshold causes a corresponding deviation of the third detection threshold. Similarly, the fourth temperature has a fourth detection threshold linked with the second detection threshold so that a deviation of the second detection threshold causes a corresponding deviation of the fourth detection threshold. The third and fourth temperature thresholds define a temperature window to test the temperature sensor for detecting a deviation of the first and second detection thresholds.

Abstract translation: 当超过温度阈值时，集成温度传感器提供阈值检测信号。 温度传感器包括用于检测具有第一检测阈值的第一温度阈值并用于检测具有第二检测阈值的第二温度阈值的电路。 电路还检测第一和第二温度阈值之间的第三温度阈值，并且检测第一和第二温度阈值之间的第四温度阈值。 第三温度阈值具有与第一检测阈值相关联的第三检测阈值，使得第一检测阈值的偏差导致第三检测阈值的相应偏差。 类似地，第四温度具有与第二检测阈值相关联的第四检测阈值，使得第二检测阈值的偏差导致第四检测阈值的相应偏差。 第三和第四温度阈值定义了温度窗口，以测试温度传感器，用于检测第一和第二检测阈值的偏差。

公开(公告)号：US20030113025A1

公开(公告)日：2003-06-19

申请号：US10251658

申请日：2002-09-19

Applicant: STMicroelectronics S.A.

Inventor： Jean-Michel Bard ,  Jean-Luc Danger ,  Lucas Hui ,  Christophe Cunat

IPC: G06K009/36 ,  G06K009/46 ,  G06K009/38

CPC classification number: H04N19/436 ,  H04N19/126 ,  H04N19/152 ,  H04N19/176 ,  H04N19/194 ,  H04N19/196 ,  H04N19/197 ,  H04N19/60

Abstract: Method of compressing a digital image signal in which a first quantization step set, which is unique for a given segment, is determined so that the number of bits needed to encode the quantized data corresponding to this segment is greater than a target value. This first quantization step set then being modified, as a priority, for the blocks of the segment for which the gain, in the course of this modification, on the reduction of the number of bits needed to encode the quantized data corresponding to the segment to which it belongs, is the highest. This modification is carried out, on as many blocks as is necessary for the number of bits of this segment to be less than or equal to the target value. Device to implement this method.

Abstract translation: 对数字图像信号进行压缩的方法，其中确定对于给定段是唯一的第一量化步长集合，使得对与该段对应的量化数据进行编码所需的位数大于目标值。 作为优先级，该第一量化步长作为优先级被修改为在该修改过程中增益对于其对应于该段的量化数据进行编码所需的位数减少的段的块 它属于哪个，是最高的。 在该段的位数小于或等于目标值所需的块上执行该修改。 设备实现这种方法。

公开(公告)号：US20030112077A1

公开(公告)日：2003-06-19

申请号：US10322205

申请日：2002-12-17

Applicant: STMicroelectronics S.A.

Inventor： Frederic Goutti ,  Vincent Rabary

IPC: H03F001/52

CPC classification number: H03F1/52

Abstract: An amplifier including first, second, and third series-connected stages, the third stage including a MOS output transistor having its source or drain forming an output terminal of the amplifier, including means for detecting the transition from a first operating state of the output transistor in which the drain current varies little with the voltage between the drain and the source to a second state in which the drain current varies substantially proportionally to the voltage between the drain and the source; and means for, upon detection of such a transition, having the voltage gain of the amplifier and/or the product between the bandwidth of the amplifier and the voltage gain of the amplifier at the upper limit frequency of the bandwidth drop.

Abstract translation: 一种包括第一，第二和第三串联级的放大器，所述第三级包括具有形成所述放大器的输出端的源极或漏极的MOS输出晶体管，包括用于检测从所述输出晶体管的第一工作状态转变的装置 其中漏极电流随着漏极和源极之间的电压变化到第二状态，其中漏极电流基本上与漏极和源极之间的电压成比例地变化; 以及用于在检测到这种转变时，具有在放大器的带宽和放大器的带宽与放大器的电压增益之间的电压增益在带宽下降的上限频率的情况下的放大器和/或乘积的电压增益的装置。