公开(公告)号：US07167400B2

公开(公告)日：2007-01-23

申请号：US10873968

申请日：2004-06-22

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C8/08

摘要： An apparatus and method for generating a control pulse for closing an active wordline in a memory device is provided. A timeout generator circuit having a time delay portion and a reset portion may be used to generate a close signal. The time delay portion may define a predetermined time delay interval. The timeout generator may be used in combination with an address transition detector in a refresh controller for a memory device. A method is given in which a control pulse is generated in response to an active mode signal, a timer measuring a predetermined time delay interval is activated in response to the control pulse, a close signal is produced in response to the expiration of the predetermined time delay interval, and the active wordline is closed in response to the close signal.

摘要翻译： 提供一种用于产生用于关闭存储器件中的有效字线的控制脉冲的装置和方法。 具有时间延迟部分和复位部分的超时发生器电路可用于产生闭合信号。 时间延迟部分可以定义预定的时间延迟间隔。 超时发生器可以与用于存储器设备的刷新控制器中的地址转换检测器组合使用。 给出了响应于有源模式信号产生控制脉冲的方法，响应于控制脉冲激活测量预定时间延迟间隔的定时器，响应于预定时间的期满而产生闭合信号 延迟间隔，并且有效字线响应于关闭信号而闭合。

公开(公告)号：US07106637B2

公开(公告)日：2006-09-12

申请号：US10754658

申请日：2004-01-08

申请人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

发明人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

IPC分类号： G11C7/00

CPC分类号： G11C8/18 ,  G11C7/22

摘要： An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

公开(公告)号：US07034507B2

公开(公告)日：2006-04-25

申请号：US10613236

申请日：2003-07-03

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： H01M10/44 ,  H01M10/46

CPC分类号： H02J7/007 ,  G01K1/02 ,  G01K1/20 ,  G01K13/00 ,  H02J7/0052

摘要： A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature.

摘要翻译： 温度感测装置可嵌入存储器电路中以便感测存储器电路的温度。 当振荡器的温度降低时，一个振荡器产生温度可变信号，随着振荡器的温度升高而频率增加，并降低频率。 温度不变振荡器产生由振荡器读取逻辑控制并指示温度感测周期的固定宽度信号。 n位计数器由温度可变信号计时，而固定宽度信号启用/禁止计数器。 计数器计数越快，固定宽度信号指示的感测周期结束时的计数值越大。 较大的计数值表示较暖的温度。 较小的计数值表示较冷的温度。

公开(公告)号：US06925024B2

公开(公告)日：2005-08-02

申请号：US10232935

申请日：2002-08-28

申请人： Simon J. Lovett ,  J. Thomas Pawlowski ,  Brian P. Higgins

发明人： Simon J. Lovett ,  J. Thomas Pawlowski ,  Brian P. Higgins

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C5/06

CPC分类号： G11C5/141

摘要： A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.

公开(公告)号：US06879538B2

公开(公告)日：2005-04-12

申请号：US10228932

申请日：2002-08-28

申请人： Simon J. Lovett ,  Thomas J. Pawlowski ,  Brian P. Higgins

发明人： Simon J. Lovett ,  Thomas J. Pawlowski ,  Brian P. Higgins

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C5/141

摘要： A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.

公开(公告)号：US06750497B2

公开(公告)日：2004-06-15

申请号：US10225423

申请日：2002-08-22

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： H01L27108

CPC分类号： G11C11/404 ,  G11C11/405 ,  G11C11/406 ,  G11C11/40603 ,  G11C2211/4065

摘要： A high-speed transparent refresh DRAM-based memory cell and architecture are disclosed. Each memory cell consists of 4 transistors configured to incorporate differential data storage (i.e., storing a true logic state and a complementary logic state), with each pair of transistors having a dual port configuration and forming one of a complementary pair of storage nodes for the memory cell. Each memory cell is coupled to 2 wordlines and 4 digit lines. Since the memory cell stores complementary data, and since a logic LOW state is rewritten to a given memory cell faster than a logic HIGH state is rewritten, the logic LOW state is rewritten and the complementary logic state is known to be a logic HIGH state. As a result, both the logic LOW and logic HIGH states are rewritten to the memory cell faster than independently writing a logic HIGH state.

公开(公告)号：US06292403B1

公开(公告)日：2001-09-18

申请号：US09521190

申请日：2000-03-07

申请人： Ashish Pancholy ,  Cathal G. Phelan ,  Simon J. Lovett

发明人： Ashish Pancholy ,  Cathal G. Phelan ,  Simon J. Lovett

IPC分类号： G11C700

CPC分类号： G11C7/1039 ,  G11C8/18 ,  G11C11/4087

摘要： A circuit including an address bus providing random addresses for a random access memory array, and a register configured to receive, store or transfer (i) a first random address from the address bus in response to a first periodic signal transition and (ii) a second random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle, and are preferably complementary to each other. In a further embodiment, the invention concerns a random access memory having an address bus providing random address information for a random access memory array, a predecoder configured to at least partially decode the random address information from the address bus, a register configured to receive, store or transfer (i) a first at least partially decoded random address from the address bus in response to a first periodic signal transition and (ii) a second at least partially decoded random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle; and a postdecoder configured to activate the random addresses in the random access memory in response to receiving the random addresses from the register.

摘要翻译： 一种包括为随机存取存储器阵列提供随机地址的地址总线的电路，以及响应于第一周期性信号转换而从地址总线接收，存储或传输（i）第一随机地址的寄存器，以及（ii） 响应于第二周期性信号转换，来自地址总线的第二随机地址，其中第一和第二周期信号转换发生在单个周期信号周期内，并且优选地彼此互补。 在另一实施例中，本发明涉及一种随机存取存储器，其具有为随机存取存储器阵列提供随机地址信息的地址总线，被配置为至少部分地从地址总线解码随机地址信息的预解码器，配置成接收， 响应于第一周期性信号转换，存储或传输（i）来自地址总线的第一至少部分解码的随机地址和（ii）响应于第二周期性信号转换的来自地址总线的第二至少部分解码的随机地址 ，其中所述第一和第二周期信号转换发生在单周期信号周期内; 以及后置解码器，被配置为响应于从寄存器接收到随机地址来激活随机存取存储器中的随机地址。

公开(公告)号：US5889416A

公开(公告)日：1999-03-30

申请号：US958500

申请日：1997-10-27

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： H03K19/0948 ,  H03K19/20 ,  H03K19/094

CPC分类号： H03K19/0948

摘要： A NAND gate including a pull-down circuit coupled to a pull-up circuit. The NAND gate is configured to drive an output signal to a high logic state at a substantially uniform slew rate regardless of the number of input signals that are in a low logic state. The pull-up circuit may include a plurality of load circuits each coupled to a corresponding one of the plurality of input signals, and a plurality of transistor circuits each comprising a plurality of transistors coupled in parallel with each other and coupled to a corresponding one of the plurality of input signals or a complement of a corresponding one of the plurality of input signals. The plurality of load circuits and the plurality of transistors may each include a p-channel MOS (PMOS) transistor. The NAND gate may be incorporated into a decoder of a synchronous or asynchronous input path circuit to generally reduce the setup and hold time window of the input path circuit.

摘要翻译： 包括耦合到上拉电路的下拉电路的NAND门。 NAND门被配置为以基本均匀的转换速率将输出信号驱动到高逻辑状态，而与处于低逻辑状态的输入信号的数量无关。 上拉电路可以包括多个负载电路，每个负载电路分别耦合到多个输入信号中的一个输入信号，以及多个晶体管电路，每个晶体管电路包括彼此并联耦合的多个晶体管，并耦合到 所述多个输入信号或所述多个输入信号中的相应一个输入信号的互补。 多个负载电路和多个晶体管可以各自包括p沟道MOS（PMOS）晶体管。 NAND门可以并入到同步或异步输入路径电路的解码器中，以大体上减少输入路径电路的建立和保持时间窗口。

公开(公告)号：US08638628B2

公开(公告)日：2014-01-28

申请号：US13480701

申请日：2012-05-25

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065

摘要： Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.

摘要翻译： 提供了系统，装置，存储器件，读出放大器和方法，诸如包括输入节点的系统，具有耦合到输入节点的栅极的第一晶体管和耦合到输入节点的另一个栅极的第二晶体管 。 在一个或多个实施例中，第二晶体管具有比第一晶体管更大的激活电压阈值，并且第一晶体管放大存在于输入节点上的信号。 在一个这样的实施例中，在第一晶体管放大信号之后，第二晶体管在第一晶体管被去激活时保持输入节点上的放大信号。

公开(公告)号：US08159896B2

公开(公告)日：2012-04-17

申请号：US12324338

申请日：2008-11-26

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G11C5/14 ,  G11C8/10 ,  G11C8/00

CPC分类号： G11C8/06 ,  G11C8/08 ,  G11C11/413

摘要： Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed are determined from external memory addresses and the row decoder for the portions of the memory array to be accessed are selectively provided with electrical power. The section of memory is then accessed. One such array includes memory section voltage supply rails having decoder circuits coupled to receive electrical power, and further includes memory section power control logic. The control logic selectively couples the memory section voltage supply rail to a primary voltage supply to provide electrical power to the memory section voltage supply rail in response to being selected based on memory addresses.

摘要翻译： 公开了用于向存储器阵列的存储器部分选择性地提供电功率的存储器，存储器阵列和方法。 存储器阵列可以通过将存储器阵列未被访问而将行解码器电路解耦以接收电力来操作。 要访问的存储器阵列的一部分由外部存储器地址确定，并且用于要访问的存储器阵列的部分的行解码器被选择性地提供电力。 然后访问内存部分。 一个这样的阵列包括具有耦合以接收电功率的解码器电路的存储器部分电压供应轨道，并且还包括存储器部分功率控制逻辑。 响应于基于存储器地址选择，控制逻辑选择性地将存储器部分电压供应轨耦合到初级电压源以向存储器部分电压供应轨提供电力。