公开(公告)号：US07106637B2

公开(公告)日：2006-09-12

申请号：US10754658

申请日：2004-01-08

申请人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

发明人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

IPC分类号： G11C7/00

CPC分类号： G11C8/18 ,  G11C7/22

摘要： An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

公开(公告)号：US06690606B2

公开(公告)日：2004-02-10

申请号：US10102221

申请日：2002-03-19

申请人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

发明人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

IPC分类号： G11C700

CPC分类号： G11C8/18 ,  G11C7/22

摘要： An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

公开(公告)号：US20190066819A1

公开(公告)日：2019-02-28

申请号：US16109092

申请日：2018-08-22

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G11C29/44 ,  G11C11/412

CPC分类号： G11C29/00 ,  G11C7/00 ,  G11C11/412 ,  G11C29/44 ,  G11C2029/4402 ,  G11C2229/763

摘要： Various embodiments, disclosed herein, include apparatus and methods of using the apparatus having a core array of memory cells arranged as data storage elements; and an array of latches to store repair information for the core array. Each latch can be structured as a static random access memory cell. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20120166862A1

公开(公告)日：2012-06-28

申请号：US13412205

申请日：2012-03-05

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G06F1/14 ,  G06F1/24

CPC分类号： H02J7/007 ,  G01K1/02 ,  G01K1/20 ,  G01K13/00 ,  H02J7/0052

摘要： A temperature sensing device can be embedded in a memory module or system in order to sense the temperature of the memory module or system. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature.

摘要翻译： 温度感测装置可嵌入存储器模块或系统中，以便感测存储器模块或系统的温度。 当振荡器的温度降低时，一个振荡器产生温度可变信号，随着振荡器的温度升高而频率增加，并降低频率。 温度不变振荡器产生由振荡器读取逻辑控制并指示温度感测周期的固定宽度信号。 n位计数器由温度可变信号计时，而固定宽度信号启用/禁止计数器。 计数器计数越快，固定宽度信号指示的感测周期结束时的计数值越大。 较大的计数值表示较暖的温度。 较小的计数值表示较冷的温度。

公开(公告)号：US08129956B2

公开(公告)日：2012-03-06

申请号：US12910287

申请日：2010-10-22

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： H01M10/44

CPC分类号： H02J7/007 ,  G01K1/02 ,  G01K1/20 ,  G01K13/00 ,  H02J7/0052

摘要： A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature.

摘要翻译： 温度感测装置可嵌入存储器电路中以便感测存储器电路的温度。 当振荡器的温度降低时，一个振荡器产生温度可变信号，随着振荡器的温度升高而频率增加，并降低频率。 温度不变振荡器产生由振荡器读取逻辑控制并指示温度感测周期的固定宽度信号。 n位计数器由温度可变信号计时，而固定宽度信号启用/禁止计数器。 计数器计数越快，固定宽度信号指示的感测周期结束时的计数值越大。 较大的计数值表示较暖的温度。 较小的计数值表示较冷的温度。

公开(公告)号：US07640413B2

公开(公告)日：2009-12-29

申请号：US11726094

申请日：2007-03-20

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G06F12/00

CPC分类号： G06F13/4234 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4243 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/413

摘要： A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

摘要翻译： 一种存储器访问模式检测电路和方法，用于检测和启动存储器件的存储器访问模式存储器访问模式检测电路接收存储器地址信号，控制信号和时钟信号，并响应于接收产生第一模式检测信号 的存储器地址信号或控制信号的第一组合。 在检测信号之后产生第一模式启动信号，以启动第一模式存储器访问操作。 响应于接收到控制信号和活动时钟信号的第二组合，存储器访问模式检测电路还产生第二模式检测信号以启动第二模式存储器访问操作并且抑制第一模式检测信号的产生，从而 取消第一模式存储器存取操作。

公开(公告)号：US20090072795A1

公开(公告)日：2009-03-19

申请号：US12273626

申请日：2008-11-19

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： H02J7/00

CPC分类号： H02J7/007 ,  G01K1/02 ,  G01K1/20 ,  G01K13/00 ,  H02J7/0052

摘要： A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature.

摘要翻译： 温度感测装置可嵌入存储器电路中以便感测存储器电路的温度。 当振荡器的温度降低时，一个振荡器产生温度可变信号，随着振荡器的温度升高而频率增加，并降低频率。 温度不变振荡器产生由振荡器读取逻辑控制并指示温度感测周期的固定宽度信号。 n位计数器由温度可变信号计时，而固定宽度信号启用/禁止计数器。 计数器计数越快，固定宽度信号指示的感测周期结束时的计数值越大。 较大的计数值表示较暖的温度。 较小的计数值表示较冷的温度。

公开(公告)号：US20080285369A1

公开(公告)日：2008-11-20

申请号：US12183646

申请日：2008-07-31

申请人： Simon J. Lovett

发明人： Simon J. Lovett

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4094

摘要： A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are selected and refreshed to the fixed logic level. A sense amplifier includes a clamping circuit adapted to connect one of a digit line and an I/O line to a fixed logic level in response to an erase signal during a refresh of the selected block of memory cells.

摘要翻译： 用于擦除多个存储器单元中的数据块的系统和方法包括将存储器件的感测电路中的数字线和I / O线中的一个钳位到固定逻辑电平。 存储器单元块的存储单元被选择并刷新到固定逻辑电平。 读出放大器包括钳位电路，其适于在刷新所选择的存储单元块期间响应于擦除信号将数字线和I / O线之一连接到固定逻辑电平。

公开(公告)号：US20080175078A1

公开(公告)日：2008-07-24

申请号：US12077577

申请日：2008-03-20

申请人： Simon J. Lovett ,  Dean Gans

发明人： Simon J. Lovett ,  Dean Gans

IPC分类号： G11C7/22

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104 ,  G11C2207/2254

摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

公开(公告)号：US07362627B2

公开(公告)日：2008-04-22

申请号：US11786551

申请日：2007-04-11

申请人： Simon J. Lovett ,  Dean Gans

发明人： Simon J. Lovett ,  Dean Gans

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104 ,  G11C2207/2254

摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。 数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。 跟踪电路响应于时钟信号以产生控制信号。 多个锁存器响应于用于锁存来自总线的数据的控制信号。 控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。 该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。 可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。 例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现 放大器 由于管理摘要的规则，本摘要不应用于解释索赔。