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    THIN FILM TRANSISTOR ARRAY PANEL
    31.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL 有权
    薄膜晶体管阵列

    公开(公告)号：US20100051957A1

    公开(公告)日：2010-03-04

    申请号：US12401959

    申请日：2009-03-11

    申请人： Dong-Gyu KIM ,  Sung-Haeng CHO ,  Hyung-Jun KIM ,  Sung-Ryul KIM ,  Yong-Mo CHOI

    发明人： Dong-Gyu KIM ,  Sung-Haeng CHO ,  Hyung-Jun KIM ,  Sung-Ryul KIM ,  Yong-Mo CHOI

    IPC分类号： H01L33/00

    CPC分类号： G02F1/136213 ,  H01L27/1255

    摘要： A thin film transistor array panel, in which a middle storage electrode and a storage electrode overlapping a drain electrode of a thin film transistor thereby forming a storage capacitance are formed. Accordingly, sufficient storage capacitance may be formed without a decrease of the aperture ratio and fight transmittance of a liquid crystal display. Also, the capacitance may be sufficiently formed through the connecting member connected to a gate metal layer.

    摘要翻译： 一种薄膜晶体管阵列面板，其中形成中间存储电极和与薄膜晶体管的漏极重叠从而形成存储电容的存储电极。 因此，可以形成足够的存储电容，而不会降低开口率并且防止液晶显示器的透射率。 此外，可以通过连接到栅极金属层的连接构件充分形成电容。

    DISPLAY SUBSTRATE
    32.
    发明申请
    DISPLAY SUBSTRATE 有权
    显示基板

    公开(公告)号：US20100006835A1

    公开(公告)日：2010-01-14

    申请号：US12486328

    申请日：2009-06-17

    申请人： Kap-Soo YOON ,  Sung-Hoon YANG ,  Sung-Ryul KIM ,  O-Sung SEO ,  Hwa-Yeul OH ,  Jae-Ho CHOI ,  Seong-Hun KIM ,  Yong-Mo CHOI

    发明人： Kap-Soo YOON ,  Sung-Hoon YANG ,  Sung-Ryul KIM ,  O-Sung SEO ,  Hwa-Yeul OH ,  Jae-Ho CHOI ,  Seong-Hun KIM ,  Yong-Mo CHOI

    IPC分类号： H01L29/786

    CPC分类号： H01L27/12 ,  H01L27/1225 ,  H01L29/7869

    摘要： A display substrate includes; a substrate, a gate electrode arranged on the substrate, a semiconductor pattern arranged on the gate electrode, a source electrode arranged on the semiconductor pattern, a drain electrode arranged on the semiconductor pattern and spaced apart from the source electrode, an insulating layer arranged on, and substantially covering, the source electrode and the drain electrode to cover the source electrode and the drain electrode, a conductive layer pattern arranged on the insulating layer and overlapped aligned with the semiconductor pattern, a pixel electrode electrically connected to the drain electrode, and a storage electrode arranged on the substrate and overlapped overlapping with the pixel electrode, the storage electrode being electrically connected to the conductive layer pattern.

    摘要翻译： 显示基板包括： 衬底，布置在衬底上的栅电极，布置在栅电极上的半导体图案，布置在半导体图案上的源电极，布置在半导体图案上并与源电极间隔开的漏电极，布置在 并且基本上覆盖源电极和漏极以覆盖源电极和漏电极，布置在绝缘层上并与半导体图案重叠的导电层图案，与漏电极电连接的像素电极，以及 存储电极，设置在所述基板上，与所述像素电极重叠地重叠，所述存储电极与所述导电层图案电连接。

    PLASMA PROCESSING APPARATUS
    33.
    发明申请
    PLASMA PROCESSING APPARATUS 有权
    等离子体加工设备

    公开(公告)号：US20090250443A1

    公开(公告)日：2009-10-08

    申请号：US12143465

    申请日：2008-06-20

    申请人： Sung Ryul KIM

    发明人： Sung Ryul KIM

    IPC分类号： B23K9/00

    CPC分类号： H01L21/67069 ,  H01L21/67265

    摘要： Provided is a plasma processing apparatus including a chamber, a lower electrode, an upper electrode, and a substrate sensor. The chamber is configured to provide a reaction space. The lower electrode is disposed at a lower region in the chamber to mount a substrate thereon. The upper electrode is disposed at an upper region in the chamber to be opposite to the lower electrode. The substrate sensor is provided on the chamber to sense the substrate. Herein, the upper electrode includes an electrode plate and an insulating plate attached on the bottom of the electrode plate, and at least one guide hole is formed in the upper electrode to guide light output from the substrate sensor toward the substrate.

    摘要翻译： 提供了一种包括室，下电极，上电极和基板传感器的等离子体处理装置。 腔室被配置成提供反应空间。 下电极设置在腔室中的下部区域以在其上安装衬底。 上部电极设置在室中的与下部电极相对的上部区域。 衬底传感器设置在腔室上以感测衬底。 这里，上电极包括安装在电极板的底部的电极板和绝缘板，并且在上电极中形成至少一个引导孔，以将从基板传感器输出的光引向基板。

    Full-stress testable memory device having an open bit line architecture and method of testing the same
    34.
    发明授权
    Full-stress testable memory device having an open bit line architecture and method of testing the same 有权
    具有开放位线架构的全压力可测试存储器件及其测试方法

    公开(公告)号：US07382668B2

    公开(公告)日：2008-06-03

    申请号：US11319247

    申请日：2005-12-27

    申请人： Ki-Won Park ,  Hong-Sun Hwang ,  Sung-Ryul Kim

    发明人： Ki-Won Park ,  Hong-Sun Hwang ,  Sung-Ryul Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/18 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/1204

    摘要： A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and a second variable control voltage to the dummy bit lines during a test mode. In accordance with a method of testing the memory device, a fixed voltage is provided to the dummy bit lines of the edge sub-arrays during a normal operation mode. However, during a test mode, the fixed voltage being applied to the dummy bit line is replaced with a supply voltage and/or a ground voltage, so that all of the sub-arrays can be equally tested.

    摘要翻译： 具有开放位线架构的全压力可测试存储器件和测试存储器件的方法。 本发明的存储器件包括虚拟位线和连接到虚拟位线的电压控制器。 电压控制器在测试模式期间交替地向虚拟位线提供第一可变控制电压和第二可变控制电压。 根据测试存储器件的方法，在正常操作模式期间，将固定电压提供给边缘子阵列的虚拟位线。 然而，在测试模式期间，施加到虚拟位线的固定电压被替换为电源电压和/或接地电压，使得可以对所有子阵列进行同样的测试。

    High burst rate write data paths for integrated circuit memory devices and methods of operating same
    35.
    发明授权
    High burst rate write data paths for integrated circuit memory devices and methods of operating same 有权
    用于集成电路存储器件的高突发速率写入数据路径及其操作方法

    公开(公告)号：US07054202B2

    公开(公告)日：2006-05-30

    申请号：US10792425

    申请日：2004-03-03

    申请人： Yun-sang Lee ,  Jung-bae Lee ,  One-gyun La ,  Sung-ryul Kim

    发明人： Yun-sang Lee ,  Jung-bae Lee ,  One-gyun La ,  Sung-ryul Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C7/1078 ,  G11C7/1027 ,  G11C2207/107

    摘要： Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

    摘要翻译： 集成电路存储器件包括被配置为并行地写入N个数据位的存储器单元阵列和被配置为从外部端子串行地接收2N个数据位的写入数据路径。 写数据路径包括2N个写入数据缓冲器，其被配置为存储2N个数据位，2N个开关和N个数据线，其被配置为将2N个开关中的至少N个连接到存储单元阵列以在其中写入N个数据位 平行。 可以提供减少数量的本地数据线和/或全局数据线。

    High vacuum apparatus for fabricating semiconductor device and method for forming epitaxial layer using the same
    36.
    发明授权
    High vacuum apparatus for fabricating semiconductor device and method for forming epitaxial layer using the same 失效
    用于制造半导体器件的高真空装置和使用其形成外延层的方法

    公开(公告)号：US06565655B2

    公开(公告)日：2003-05-20

    申请号：US09803859

    申请日：2001-03-12

    申请人： Chul-Ju Hwang ,  Sung-Ryul Kim ,  Jae-Kyun Park

    发明人： Chul-Ju Hwang ,  Sung-Ryul Kim ,  Jae-Kyun Park

    IPC分类号： C30B2514

    CPC分类号： C23C16/45502 ,  C23C16/4401 ,  C23C16/45563 ,  C23C16/45591 ,  C23C16/45593 ,  C30B25/14 ,  Y10T117/10

    摘要： A high vacuum apparatus for fabricating a semiconductor device includes a reactive chamber provided with an inlet and an outlet for a reactive gas, a suscepter installed in the reactive chamber for mounting the semiconductor thereon and a vacuum pump connected with the outlet to make the inside of the reactive chamber to put in a high vacuum state, wherein a gas injector of the reactive gas inlet is directed downward of the semiconductor device so that the initial gas flowing of the reactive gas injected from the reactive gas inlet does not directly pass the upper portion of the semiconductor substrate mounted on the suscepter. Since the reactive gas is prevented from cooling and condensing at the upper surface of the semiconductor substrate, defective proportion of the semiconductor device can be remarkably reduced. In addition, the gas outlet is installed at the portion where the reactive gas is satisfactorily cooled and condensed and the vacuum pump is connected with the gas outlet, so that the cooled and condensed contaminant generating source is quickly removed, and thus the defective proportion of the semiconductor device can be considerably reduced.

    摘要翻译： 用于制造半导体器件的高真空装置包括设置有用于反应气体的入口和出口的反应室，安装在反应室中的用于将半导体安装在其上的阻塞器和与出口连接的真空泵， 所述反应室进入高真空状态，其中所述反应气体入口的气体喷射器被引导到所述半导体器件的下方，使得从所述反应气体入口喷射的反应气体的初始气体流不直接通过所述上部 的半导体衬底。 由于防止反应性气体在半导体衬底的上表面处冷却和冷凝，所以可以显着地减少半导体器件的不合格率。 此外，气体出口安装在反应气体被令人满意地冷却和冷凝的部分处，并且真空泵与气体出口连接，使得冷却和冷凝的污染物发生源被快速去除，因此，缺陷比例 可以大大减少半导体器件。

    Address generating and decoding circuit for use in burst-type random access memory device having a double data rate, and an address generating method thereof
    37.
    发明授权
    Address generating and decoding circuit for use in burst-type random access memory device having a double data rate, and an address generating method thereof 有权
    用于具有双重数据速率的脉冲串型随机存取存储器件中的地址产生和解码电路及其地址产生方法

    公开(公告)号：US06272065B1

    公开(公告)日：2001-08-07

    申请号：US09368391

    申请日：1999-08-04

    申请人： Sung-Ryul Kim

    发明人： Sung-Ryul Kim

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1021 ,  G11C8/18

    摘要： Disclosed is a burst-type random access memory device with a double data rate scheme, in which at least two data is inputted/outputted to/from the memory device during a clock cycle. In the burst-type random access memory device, a first address generator is further provided, which generates a sequence of addresses in response to an externally applied initial address, wherein the first addresses correspond to a first half period of the clock cycle during a burst mode of operation, respectively. And, in the memory device, a second address generator is furthermore provided, which receives the addresses from the first address generator and generates a sequence of addresses in accordance with burst information signals each indicative of a burst length and a type of the burst mode of operation, wherein the second addresses correspond to a second half period of the clock cycle during the burst mode of operation, respectively. According to the burst-type random access memory device, the second address generator is implemented such that the address for the second half period of a clock cycle is automatically generated in accordance with the burst length and mode. With the configuration, the access of the burst-type random access memory device with the DDR scheme can be speeded up.

    摘要翻译： 公开了一种具有双数据速率方案的突发式随机存取存储器件，其中在时钟周期期间至少两个数据被输入/输出到存储器件。 在脉冲串式随机存取存储器件中，还提供第一地址发生器，其响应于外部施加的初始地址产生地址序列，其中第一地址对应于在突发期间的时钟周期的前半个周期 分别为操作模式。 而且，在存储装置中，还提供第二地址发生器，其接收来自第一地址发生器的地址，并根据突发信息信号生成地址序列，每个突发信息信号指示突发长度和突发模式的类型 操作，其中第二地址分别对应于脉冲串操作期间的时钟周期的第二半周期。 根据突发型随机存取存储器件，第二地址发生器被实现为使得根据突发长度和模式自动生成时钟周期的后半段的地址。 利用该配置，可以加速具有DDR方案的突发型随机存取存储器件的访问。