公开(公告)号：US5479370A

公开(公告)日：1995-12-26

申请号：US376439

申请日：1995-01-23

申请人： Tohru Furuyama ,  Donald C. Stark

发明人： Tohru Furuyama ,  Donald C. Stark

IPC分类号： G11C11/401 ,  G11C8/04 ,  G11C11/405 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00 ,  G11C11/34

CPC分类号： G11C8/04

摘要： A semiconductor memory of this invention comprises a memory cell array containing memory cells arranged in matrix form, word lines each connected to all the memory cells in the same row, and bit lines each connected to all the memory cells in the same column, a shift register containing a plurality of stages of shift circuits which is used as a serial address pointer for serially specifying the addresses of actually used rows and/or columns in the memory cell array, a bypass circuit capable of forming a bypass for the shift circuit at a given stage of the shift register, and a bypass control circuit for determining whether or not a bypass is to be formed by the bypass circuit.

摘要翻译： 本发明的半导体存储器包括存储单元阵列，该存储单元阵列包含以矩阵形式布置的存储单元，每行连接到同一行中的所有存储单元的字线以及连接到同一列中的所有存储单元的位线， 寄存器，其包含用于串行地指定存储单元阵列中的实际使用的行和/或列的地址的串行地址指针的多级移位电路，能够在一个位置上形成用于移位电路的旁路的旁路电路 移位寄存器的给定级，以及用于判断旁路是否由旁路电路形成的旁路控制电路。

公开(公告)号：US5410512A

公开(公告)日：1995-04-25

申请号：US64438

申请日：1993-05-21

申请人： Satoru Takase ,  Tohru Furuyama ,  Donald C. Stark ,  Natsuki Kushiyama ,  Kiyofumi Sakurai ,  Hiroyuki Noji ,  Shigeo Ohshima

发明人： Satoru Takase ,  Tohru Furuyama ,  Donald C. Stark ,  Natsuki Kushiyama ,  Kiyofumi Sakurai ,  Hiroyuki Noji ,  Shigeo Ohshima

IPC分类号： G11C11/401 ,  G06F12/02 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407 ,  G11C11/41

CPC分类号： G11C7/1021

摘要： A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.

摘要翻译： 半导体存储器件包括形成在芯片中的硅芯片和子阵列。 在每个子阵列中，布置成矩阵形式的存储器单元，为每个子阵列的各行提供的字线，以及为每个子阵列的各列提供的位线。 此外，在芯片中，放置用于放大从存储单元读出的数据的放大器组用于各个子阵列。 连接到相应位线的放大器设置在放大器组中，并且放大器各自具有连续保持从存储单元读出的数据的功能。

公开(公告)号：US5294776A

公开(公告)日：1994-03-15

申请号：US926432

申请日：1992-08-10

申请人： Tohru Furuyama

发明人： Tohru Furuyama

IPC分类号： H01L21/66 ,  G01R31/28 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/108 ,  G01R31/00

CPC分类号： G01R31/2856 ,  H01L21/76886 ,  H01L23/528 ,  G01R31/2831 ,  G01R31/2863 ,  H01L2924/0002

摘要： Since the power-supply and/or signal-transmission wiring layers connected to the semiconductor chip regions are formed, each individual integrated circuit can be burned in on the semiconductor wafer and, in other words, an integrated circuit can be burned in on a wafer level. The integrated circuit can thus be burned in at the end of a wafer process. An assembled semiconductor device is subjected to a high temperature or a high humidity, for checking the reliability of the assembled device.

摘要翻译： 由于形成了连接到半导体芯片区域的电源和/或信号传输布线层，所以可以在半导体晶片上烧录各个集成电路，换句话说，集成电路可以在晶圆上燃烧 水平。 因此，集成电路可以在晶圆工艺结束时燃烧。 组装的半导体器件经受高温或高湿度，用于检查组装的器件的可靠性。

公开(公告)号：US5023476A

公开(公告)日：1991-06-11

申请号：US299424

申请日：1989-01-23

申请人： Yohji Watanabe ,  Tohru Furuyama

发明人： Yohji Watanabe ,  Tohru Furuyama

IPC分类号： H01L21/66 ,  G05F1/46 ,  G06F1/04 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  H01L21/822 ,  H01L27/04

CPC分类号： G11C5/147 ,  G05F1/465 ,  H01L2924/0002

摘要： An integrated semiconductor device is disclosed which has a highly-integrated circuit formed on a substrate. A constant voltage generator is connected to the integrated circuit, for receiving an externally-supplied d.c. power supply voltage to produce a regulated d.c. voltage, the potential level of which is lower than the external power supply voltage and remains substantially constant irrespective of the external power supply voltage. A mode-change controller is connected in parallel with the voltage generator, for supplying the output d.c. voltage of the voltage generator to the integrated circuit as an internal power supply voltage in a normal operation mode. When the device is subjected to an accelerated test using an increased power supply voltage, a switching transistor is rendered conductive under the control of a control circuit, thereby allowing the external power supply voltage to be directly applied to the integrated circuit.

公开(公告)号：US4967395A

公开(公告)日：1990-10-30

申请号：US304173

申请日：1989-01-31

申请人： Yohji Watanabe ,  Tohru Furuyama

发明人： Yohji Watanabe ,  Tohru Furuyama

IPC分类号： G11C11/409 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094

CPC分类号： G11C11/4076 ,  G11C11/4074 ,  G11C11/4094

摘要： An amplitude limiting circuit is arranged in a DRAM with (1/2) VCC precharge to equalize an amplitude between a precharge voltage and an "H" level output of each pair of bit lines charged and discharged in an active cycle with an amplitude of the precharge voltage and an "L" level output of each pair of bit lines.

摘要翻译： 幅度限制电路被布置在具有（1/2）VCC预充电的DRAM中，以使得在活动周期中充电和放电的每对位线的预充电电压和“H”电平输出之间的幅度相等， 每对位线的预充电电压和“L”电平输出。

公开(公告)号：US4841483A

公开(公告)日：1989-06-20

申请号：US130568

申请日：1987-12-09

申请人： Tohru Furuyama

发明人： Tohru Furuyama

IPC分类号： G11C7/18 ,  G11C11/56

CPC分类号： G11C7/18 ,  G11C11/565 ,  G11C16/24

摘要： The invention provides a semiconductor memory having a plurality of memory cells and a bit line connected to the memory cells comprising, the bit line being formed of a plurality of sub-bit lines, switch means for interconnecting and disconnecting the sub-bit lines, reference potential means for storing reference potentials, and sense amplifier means for comparing the output of an addressed memory cell with the reference potentials, whereby the memory is capable of storing n-valued data using n different storage potentials.

公开(公告)号：US4833341A

公开(公告)日：1989-05-23

申请号：US31263

申请日：1987-03-30

申请人： Yohji Watanabe ,  Tohru Furuyama

发明人： Yohji Watanabe ,  Tohru Furuyama

IPC分类号： H01L21/66 ,  G05F1/46 ,  G06F1/04 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  H01L21/822 ,  H01L27/04

CPC分类号： G11C5/147 ,  G05F1/465 ,  H01L2924/0002

摘要： An integrated semiconductor device is disclosed which has a highly-integrated circuit formed on a substrate. A constant voltage generator is connected to the integrated circuit, for receiving an externally-supplied d.c. power supply voltage to produce a regulated d.c. voltage, the potential level of which is lower than the external power supply voltage and remains substantially constant irrespective of the external power supply voltage. A mode-change controller is connected in parallel with the voltage generator, for supplying the output d.c. voltage of the voltage generator to the integrated circuit as an internal power supply voltage in a normal operation mode. When the device is subjected to an accelerated test using an increased power supply voltage, a switching transistor is rendered conductive under the control of a control circuit, thereby allowing the external power supply voltage to be directly applied to the integrated circuit.

摘要翻译： 公开了一种集成半导体器件，其具有形成在衬底上的高度集成电路。 恒压发生器连接到集成电路，用于接收外部提供的直流电。 电源电压产生调节直流。 电压，其电位电平低于外部电源电压，并且与外部电源电压无关地保持大致恒定。 模式变化控制器与电压发生器并联连接，用于提供输出直流。 电压发生器的电压作为正常工作模式下的内部电源电压。 当使用增加的电源电压对器件进行加速测试时，在控制电路的控制下使开关晶体管导通，从而允许外部电源电压直接施加到集成电路。

公开(公告)号：US4733374A

公开(公告)日：1988-03-22

申请号：US844626

申请日：1986-03-27

申请人： Tohru Furuyama ,  Shigeyoshi Watanabe ,  Tatsuo Ikawa

发明人： Tohru Furuyama ,  Shigeyoshi Watanabe ,  Tatsuo Ikawa

IPC分类号： H01L27/108 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C8/14 ,  G11C11/408 ,  G11C11/4097

摘要： A semiconductor memory device has N sense amplifiers each having first and second input terminals, N first memory cells, N second memory cells, N first bit lines each of which is connected to the first memory cells of the same column and connected to the first input terminal of one of the sense amplifiers, and N second bit lines each of which is connected to the second memory cells of the same column and connected to the second input terminal of one of the sense amplifiers. The first memory cells are formed in a first memory cell area and the second memory cells are formed in a second memory cell area arranged adjacent to the first memory cell area and on the same side as the first memory cell area with respect to the sense amplifiers.

摘要翻译： 半导体存储器件具有N个读出放大器，每个读出放大器具有第一和第二输入端，N个第一存储单元，N个第二存储器单元，N个第一位线，每个第一位线连接到同一列的第一存储器单元并连接到第一输入端 一个读出放大器的一个端子，以及N个第二位线，每个第二位线连接到同一列的第二存储器单元并连接到一个读出放大器的第二输入端。 第一存储器单元形成在第一存储单元区域中，并且第二存储器单元形成在与第一存储单元区域相邻布置的第二存储器单元区域中，并且与第一存储器单元区域相对于读出放大器 。

公开(公告)号：US4368529A

公开(公告)日：1983-01-11

申请号：US197950

申请日：1980-10-17

申请人： Tohru Furuyama

发明人： Tohru Furuyama

IPC分类号： G11C11/409 ,  G11C11/4094 ,  G11C11/40

CPC分类号： G11C11/4094

摘要： A semiconductor matrix circuit includes first and second matrix arrays of semiconductor memory cells, a plurality of sense amplifiers each having a flip-flop circuit, a plurality of first bit lines each commonly connected to memory cells in the same row of the first matrix array and also connected respectively to first bi-stable output terminals of the flip-flop circuits, and a plurality of second bit lines each commonly connected to memory cells in the same row of the second matrix array and also connected respectively to second bi-stable output terminals of the flip-flop circuits. Switching MOS transistors are each connected between the first and second bi-stable output terminals of a corresponding one of the flip-flop circuits. After a reading operation, the first and second bit lines are selectively set to high and low potential levels V.sub.D and V.sub.S, and subsequently all the switching MOS transistors are rendered conductive to set the potential on all the bit lines to an intermediate level (V.sub.D +V.sub.S)/2.

摘要翻译： 半导体矩阵电路包括半导体存储单元的第一和第二矩阵阵列，多个读出放大器，每个具有触发器电路，多个第一位线，每个第一位线共同连接到第一矩阵阵列的同一行中的存储器单元;以及 还分别连接到触发器电路的第一双稳态输出端子，以及多个第二位线，每个第二位线共同连接到第二矩阵阵列的同一行中的存储器单元，并且还分别连接到第二双稳态输出端子 的触发器电路。 开关MOS晶体管分别连接在相应的一个触发器电路的第一和第二双稳态输出端子之间。 在读取操作之后，第一和第二位线被选择性地设置为高电平和低电位电平VD和VS，随后所有开关MOS晶体管导通，以将所有位线上的电位设置为中间电平（VD + VS）/ 2。

公开(公告)号：US20080250231A1

公开(公告)日：2008-10-09

申请号：US12059160

申请日：2008-03-31

申请人： Hiroki TAGAWA ,  Tohru FURUYAMA ,  Nobu MATSUMOTO

发明人： Hiroki TAGAWA ,  Tohru FURUYAMA ,  Nobu MATSUMOTO

IPC分类号： G06F9/44 ,  G06F9/30

CPC分类号： G06F8/53 ,  G06F8/52

摘要： A program conversion apparatus includes: a code analyzing section configured to analyze an A binary code executable in an A processor in order to convert the A binary code into a program code for a B processor; a instruction function extracting section configured to extract a predetermined instruction function for the B processor which corresponds to a predetermined instruction for the A processor obtained by the analysis performed by the code analyzing section; and a translator section configured to generate a source code for the B processor from the A binary code, by rewriting the predetermined instruction for the A processor to the predetermined instruction function extracted by the instruction function extracting section.

摘要翻译： 程序转换装置包括：代码分析部件，被配置为分析在A处理器中可执行的A二进制代码，以将A二进制代码转换为用于B处理器的程序代码; 指令功能提取部，被配置为提取对应于由代码分析部执行的分析获得的用于所述A处理器的预定指令的B处理器的预定指令功能; 以及翻译器部分，被配置为通过将用于A处理器的预定指令重写为由指令功能提取部分提取的预定指令函数来从A二进制代码生成用于B处理器的源代码。