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    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    31.
    发明申请
    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20240422989A1

    公开(公告)日：2024-12-19

    申请号：US18223043

    申请日：2023-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

    IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    32.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20240413225A1

    公开(公告)日：2024-12-12

    申请号：US18811736

    申请日：2024-08-21

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

    IPC: H01L29/66 ,  H01L21/762

    Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

    THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE
    34.
    发明申请
    THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE 有权

    公开(公告)号：US20240413136A1

    公开(公告)日：2024-12-12

    申请号：US18223539

    申请日：2023-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tsung-Kai Yu ,  Chen-Hsiao Wang ,  Yi-Feng Hsu ,  Kai-Kuang Ho

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

    Abstract: The present invention provides a 3D integrated circuit structure formed by stacking semiconductor structures. The semiconductor structures form a multi-die heterogeneous 3D packaging by direct bonding the bonding pads of re-distribution layers. The same or different dies are used to produce the semiconductor structures through the back-end packaging process, and then hybrid bonding technology is used to stack and interconnect the semiconductor structures. The position of the bonding pad can be redefined by re-distribution layer, thereby overcoming the limitations of chip bonding pad position, chip size and quantity.

    RESISTIVE SWITCHING DEVICE AND FABRICATION METHOD THEREOF
    36.
    发明申请
    RESISTIVE SWITCHING DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20240407274A1

    公开(公告)日：2024-12-05

    申请号：US18219717

    申请日：2023-07-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode; and a cone-shaped top electrode on the resistive switching layer. The cone-shaped top electrode can produce increased and concentrated electric field during operation, which facilitates the filament forming process.

    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    37.
    发明申请
    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20240407273A1

    公开(公告)日：2024-12-05

    申请号：US18218602

    申请日：2023-07-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Hsiang-Hung Peng ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: A resistive memory device includes a first dielectric layer, a via connection structure, and a resistive switching element. The via connection structure is disposed in the first dielectric layer, and the resistive switching element is disposed on the via connection structure and the first dielectric layer. The resistive switching element includes a titanium bottom electrode, a titanium top electrode, and a variable resistance material. The titanium top electrode is disposed above the titanium bottom electrode, and the variable resistance material is sandwiched between the titanium bottom electrode and the titanium top electrode in a vertical direction. The variable resistance material is directly connected with the titanium bottom electrode and the titanium top electrode, and the titanium bottom electrode is directly connected with the via connection structure.

    LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY
    38.
    发明申请
    LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20240404587A1

    公开(公告)日：2024-12-05

    申请号：US18218025

    申请日：2023-07-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Chun-Yen Tseng

    IPC: G11C11/412 ,  G11C5/06

    Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

    SEMICONDUCTOR MEMORY DEVICE
    40.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20240397838A1

    公开(公告)日：2024-11-28

    申请号：US18795158

    申请日：2024-08-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Ching Hsu

    IPC: H10N70/00 ,  H10N70/20

    Abstract: A semiconductor memory device includes a substrate; a first dielectric layer on the substrate; and bottom electrodes on the first dielectric layer. The bottom electrodes are arranged equidistantly in a first direction and extend along a second direction. A second dielectric layer is disposed on the first dielectric layer. Top electrodes are disposed in the second dielectric layer and arranged at intervals along the second direction. Each top electrode includes a lower portion located around each bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrodes and around the tapered upper portion. A resistive-switching layer is disposed between a sidewall of each bottom electrode and a sidewall of the lower portion and between the third dielectric layer and a sidewall of the tapered upper portion. An air gap is disposed in the third dielectric layer.

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