公开(公告)号：US20180062400A1

公开(公告)日：2018-03-01

申请号：US15488525

申请日：2017-04-17

Applicant: VIA Technologies, Inc.

Inventor： Tze-Shiang Wang

IPC: H02J7/00

CPC classification number: H02J7/045 ,  H02J2007/0096

Abstract: A charger and a power delivery control chip and a charging method thereof are provided. Resistance values of equivalent resistances corresponding to a power supply bus are calculated according to a charging current and voltage sensing signals respectively provided by chips of a first connector and a second connector. A charging voltage supplied to the power supply bus is adjusted according to a target charging voltage, a current charging current, and variations of the resistance values of the equivalent resistances corresponding to the power supply bus.

公开(公告)号：US09817725B2

公开(公告)日：2017-11-14

申请号：US14514733

申请日：2014-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Chin-Yin Tsai ,  Yi-Lin Lai

IPC: G06F11/14 ,  G06F12/02

CPC classification number: G06F11/1469 ,  G06F11/1441 ,  G06F11/1451 ,  G06F12/0246 ,  G06F2201/84 ,  G06F2212/1008 ,  G06F2212/7201 ,  G06F2212/7207 ,  G06F2212/7209

Abstract: A flash memory control technique with high reliability is provided. A flash memory controller provides a volatile storage area for temporary storage of logical-to-physical address mapping data between a host and a flash memory as well as error detection codes encoded from the logical-to-physical address mapping data. When reading from the volatile storage area, the microcontroller of the flash memory controller is configured to perform an error detection procedure based on the error detection codes. The microcontroller is further configured to restore the logical-to-physical address mapping data in the volatile storage area based on a backup of the logical-to-physical address mapping data.

公开(公告)号：USD800592S1

公开(公告)日：2017-10-24

申请号：US29587916

申请日：2016-12-16

Applicant: VIA TECHNOLOGIES, INC.

Designer： Jui-Cheng Jean ,  Ya-Ling Chen

公开(公告)号：US09798898B2

公开(公告)日：2017-10-24

申请号：US14884525

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/00 ,  G06F21/72 ,  G06F9/30 ,  H04L9/08 ,  G06F21/74 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/60 ,  G06F21/71 ,  H04L9/06

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0827 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor conditionally grants a request to switch from a normal execution mode in which encrypted instructions cannot be executed, into a secure execution mode (SEM). Thereafter, the microprocessor executes a plurality of instructions, including a store-key instruction to write a set of one or more cryptographic key values into a secure memory of the microprocessor. After fetching an encrypted program from an instruction cache, the microprocessor decrypts the encrypted program into plaintext instructions using decryption logic within the microprocessor's instruction-processing pipeline.

公开(公告)号：US20170277471A1

公开(公告)日：2017-09-28

申请号：US15166268

申请日：2016-05-27

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Huei Huang ,  Yi-Lin Lai

IPC: G06F3/06 ,  G06F11/07 ,  G06F12/10

CPC classification number: G06F3/0647 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F3/0685 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G06F12/1009 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned a group read-count value. An adjustment of the group read-count values is triggered by a read command of a host. When one read-count value of the group read-count values exceeds a preset range, the controller performs a scan operation to non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the read-count value, so as to check a number of error bits. The controller decides whether to perform a storage block data-moving operation to the non-volatile storage block corresponding to the corresponding logical block address group based on results of the scan operation.

公开(公告)号：US09646000B2

公开(公告)日：2017-05-09

申请号：US14144557

申请日：2013-12-31

Applicant: VIA Technologies, Inc.

Inventor： Guo-Feng Zhang ,  Yi-Fei Zhu

IPC: G06F17/30 ,  G06F17/28 ,  G06F17/27

CPC classification number: G06F17/28 ,  G06F17/2705 ,  G06F17/271 ,  G06F17/2785 ,  G06F17/30312 ,  G06F17/30401 ,  G06F17/30864

Abstract: A search method, a search system, and a natural language comprehension system are provided. The search system includes a structured database and a search engine. The structured database stores a plurality of records, each of which has a title field and a content field. The title field includes at least one sub-field, and each sub-field includes an indication field and a value field. The indication field stores indication data, the value field stores value data, and the content field stores detailed content data. The search engine conducts a full-text search to the records in the structured database according to a keyword derived from a user's request formation, and a search result is transmitted to a knowledge comprehension assistance module, so as to recognize the user's intention. After the user's intention is recognized, information associated with the recognized user's intention is transmitted back to the user.

公开(公告)号：US20170098081A1

公开(公告)日：2017-04-06

申请号：US15380762

申请日：2016-12-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn HENRY

IPC: G06F21/57 ,  G06F13/42 ,  H04L9/32 ,  G06F9/44 ,  H04L29/06

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F13/4282 ,  G06F21/554 ,  G06F2221/2107 ,  H04L9/3242

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of an APIC access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

公开(公告)号：US20170098079A1

公开(公告)日：2017-04-06

申请号：US15380661

申请日：2016-12-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY

IPC: G06F21/57 ,  G06F13/42 ,  H04L9/32 ,  G06F9/44 ,  H04L29/06

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F13/24 ,  G06F13/4282 ,  G06F21/554 ,  G06F2221/2107 ,  H04L9/06 ,  H04L9/0618 ,  H04L9/0869 ,  H04L9/3231 ,  H04L9/3242 ,  H04L63/0435 ,  H04L63/0876 ,  H04L63/123

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of an operating system call. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

公开(公告)号：US20170098078A1

公开(公告)日：2017-04-06

申请号：US15380063

申请日：2016-12-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY

IPC: G06F21/57 ,  H04L9/32 ,  G06F13/24 ,  G06F13/42 ,  G06F9/44 ,  H04L29/06

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F13/24 ,  G06F13/4282 ,  G06F21/554 ,  G06F2221/2107 ,  H04L9/06 ,  H04L9/0618 ,  H04L9/0869 ,  H04L9/3231 ,  H04L9/3242 ,  H04L63/0435 ,  H04L63/0876 ,  H04L63/123

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a PCI Express access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

公开(公告)号：US20170098077A1

公开(公告)日：2017-04-06

申请号：US15380015

申请日：2016-12-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY

IPC: G06F21/57 ,  H04L9/32 ,  G06F13/24 ,  G06F13/42 ,  G06F9/44 ,  H04L29/06

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F13/24 ,  G06F13/4282 ,  G06F21/554 ,  G06F2221/2107 ,  H04L9/06 ,  H04L9/0618 ,  H04L9/0869 ,  H04L9/3231 ,  H04L9/3242 ,  H04L63/0435 ,  H04L63/0876 ,  H04L63/123

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a change in virtual memory mapping. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.