公开(公告)号：US06212002B1

公开(公告)日：2001-04-03

申请号：US09329109

申请日：1999-06-09

Applicant: Wen-Chin Lin ,  Ying-Tso Lin ,  Lih-Gen Sheu

Inventor： Wen-Chin Lin ,  Ying-Tso Lin ,  Lih-Gen Sheu

IPC: H01S300

CPC classification number: H04B10/2537 ,  H01S5/026 ,  H01S5/146 ,  H01S5/50

Abstract: The invention provides an optical amplifying system having a structure with two amplification levels to amplify received optical signals. The optical amplifying system includes a Michelson interferometer, a preamplifier, and a post amplifier. In the preamplifier and the post-amplifier, respectively have a light pumping source, a wavelength multiplexer, and an optical gain media. The Michelson interferometer includes an optical coupler and an optical grating set composed of a pair of optical gratings. The optical gratings are located different optical passes, and its central wavelength is equal to the intended wavelength. The optical grating can be formed on a piezoelectric substrate or an electrothermal substrate so that the central wavelength can be changed by applying stress or heat. The intended wavelength reflected by the Michelson interferometer can therefore be adjusted. The preamplifier and the post-amplifier are coupled together through the optical coupler of the Michelson interferometer. Furthermore, an isolator can also be coupled between the preamplifier and the Michelson interferometer so as to avoid the backward propagation noise.

Abstract translation: 本发明提供一种具有两个放大电平结构以放大接收到的光信号的光放大系统。 该光放大系统包括迈克尔逊干涉仪，前置放大器和后置放大器。 在前置放大器和后置放大器中，分别具有光泵浦源，波长多路复用器和光增益介质。 迈克尔逊干涉仪包括光耦合器和由一对光栅组成的光栅集。 光栅位于不同的光通道，其中心波长等于预期波长。 光栅可以形成在压电基板或电热基板上，使得可以通过施加应力或热来改变中心波长。 因此可以调整由迈克尔逊干涉仪反射的预期波长。 前置放大器和后置放大器通过Michelson干涉仪的光耦合器耦合在一起。 此外，隔离器也可以耦合在前置放大器和迈克尔逊干涉仪之间，以避免反向传播噪声。

公开(公告)号：US06185797B1

公开(公告)日：2001-02-13

申请号：US09376306

申请日：1999-08-18

Applicant: Chin-Kuo Lan ,  Tsung-Min Kung ,  Wen-Chin Lin ,  Hung-Te Hou

Inventor： Chin-Kuo Lan ,  Tsung-Min Kung ,  Wen-Chin Lin ,  Hung-Te Hou

IPC: A44B1125

CPC classification number: A44B11/12 ,  Y10T24/45696 ,  Y10T24/45712

Abstract: A lift-control buckle, which includes a female buckle member and a male buckle member respectively fastened to two distal ends of a belt, and a locking plate pivoted to two upright blocks inside the female buckle for locking the male buckle member after insertion of the male buckle member into a receiving space defined within the male buckle member between the upright blocks, wherein the locking plate has two springy side arms respectively supported on a respective step inside the female buckle member and stopped against the upright blocks for automatically returning the locking plate to the locking position after each unlocking operation.

Abstract translation: 升降控制带扣，其包括分别固定在皮带的两个远端上的阴扣构件和公扣构件以及锁定板，所述锁定板枢转到所述阴扣内的两个直立块，用于在插入所述插头后锁定所述公扣构件 公扣构件插入到位于直立块之间的公扣构件内的接收空间中，其中锁定板具有分别支撑在母扣构件内部的相应台阶上的两个弹性侧臂，并且抵靠在直立块上以自动返回锁定板 在每次解锁操作之后到锁定位置。

公开(公告)号：US06167631A

公开(公告)日：2001-01-02

申请号：US09321855

申请日：1999-05-28

Applicant: Wen Chin Lin

Inventor： Wen Chin Lin

IPC: G01C916

CPC classification number: G01C9/16

Abstract: A plummet level for checking the horizontal state of a surface and locating two vertically spaced points generally required by wood working in most interior decorative works. The plummet level includes a rectangular main body divided into front and rear compartments for balance beam and weight-loaded swing link, respectively, to mount therein on a central pivot shaft. Two long clear windows are separately provided on walls of the main body facing the balance beam and the swing link. A plurality of spaced and parallel check lines horizontally extend a full length of the windows. A user may visually overlap one of the check lines on the windows and a reference level/vertical line on the balance beam/swing link to check a working surface for its horizontal or vertical state. Two extensible links are connected to two ends of the main body with four right-angled corners defined by an end plate of each extensible link always in alignment with four side walls of the main body, so that the plummet level may be easily extended to conveniently locate and mark a horizontally or vertically corresponding point at a distance longer than the main body of the plummet level.

Abstract translation: 用于检查表面的水平状态并定位通常在大多数室内装饰作品中木材加工所需的两个垂直间隔的位置的垂直等级。 直立式液位计包括一个矩形主体，分别分成用于平衡梁和重量的摆动连杆的前后舱，以便将其安装在中心枢轴上。 两个长的透明窗口分别设置在主体的面向平衡梁和摆动连杆的墙壁上。 多个间隔开且平行的检查线水平地延伸窗口的全长。 用户可以视觉地重叠窗口上的支线和其中一条支撑线/摆动连杆上的基准水平/垂直线，以检查工作表面的水平或垂直状态。 两个可延伸的连接件连接到主体的两端，四个直角由每个可伸缩连杆的端板限定，总是与主体的四个侧壁对准，使得倾斜程度可以容易地伸长到方便 定位并标记一个水平或垂直对应的点，距离远于对等体的主体。

公开(公告)号：US08759219B2

公开(公告)日：2014-06-24

申请号：US13012211

申请日：2011-01-24

Applicant: Ya-Hsueh Hsieh ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

Inventor： Ya-Hsueh Hsieh ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

IPC: H01L21/331 ,  H01L21/463

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L29/4966 ,  H01L29/517

Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.

Abstract translation: 提供了制造半导体部件的平面化方法。 介电层形成在衬底之上并在其中限定沟槽。 在沟槽中依次形成阻挡层和金属层。 通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。 第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。 通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。 第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

公开(公告)号：US08475579B2

公开(公告)日：2013-07-02

申请号：US12825583

申请日：2010-06-29

Applicant: Chien-Ming Chen ,  Shun-Te Lin ,  Chien-Wen Lee ,  Wen-Chin Lin

Inventor： Chien-Ming Chen ,  Shun-Te Lin ,  Chien-Wen Lee ,  Wen-Chin Lin

IPC: C09D11/02

CPC classification number: C09D11/324

Abstract: A black ink composition is provided. The black ink composition includes a dispersive black colorant; less than 1 wt % of a glycol ether compound based on total weight of the black ink composition; a solvent; and water. The black ink composition of the present invention is free of surfactants and has excellent compatibility with a nozzle, and thus provides good smoothness in printing and high-quality image.

Abstract translation: 提供黑色油墨组合物。 黑色油墨组合物包括分散黑色着色剂; 小于1重量％的基于黑色油墨组合物的总重量的二醇醚化合物; 溶剂; 和水。 本发明的黑色油墨组合物不含表面活性剂并且与喷嘴具有优异的相容性，因此提供良好的印刷平滑性和高品质图像。

公开(公告)号：US20120187563A1

公开(公告)日：2012-07-26

申请号：US13012211

申请日：2011-01-24

Applicant: Ya-Hsueh HSIEH ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

Inventor： Ya-Hsueh HSIEH ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

IPC: H01L23/532 ,  H01L21/28

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L29/4966 ,  H01L29/517

Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.

Abstract translation: 提供了制造半导体部件的平面化方法。 介电层形成在衬底之上并在其中限定沟槽。 在沟槽中依次形成阻挡层和金属层。 通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。 第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。 通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。 第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

公开(公告)号：USD650514S1

公开(公告)日：2011-12-13

申请号：US29387543

申请日：2011-03-15

Applicant: Chih-Chen Lin ,  Wen-Chin Lin ,  Shuh-Hwar Yahn

Designer： Chih-Chen Lin ,  Wen-Chin Lin ,  Shuh-Hwar Yahn

公开(公告)号：US20110059590A1

公开(公告)日：2011-03-10

申请号：US12945860

申请日：2010-11-14

Applicant: Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

Inventor： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

IPC: H01L21/02

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1691

Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

Abstract translation: 一种相变存储器结构及其形成方法，所述方法包括提供包括导电区域的衬底; 在间隔物的上部形成具有部分暴露的侧壁区域的间隔物，其限定相变存储元件接触区域; 并且其中所述间隔件底部部分与所述导电区域重叠。 这两种方法都可以减少相变存储元件的有效面积，从而减少所需的相变电流。

公开(公告)号：US07858980B2

公开(公告)日：2010-12-28

申请号：US10791607

申请日：2004-03-01

Applicant: Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

Inventor： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

IPC: H01L29/18

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1691

Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

Abstract translation: 一种相变存储器结构及其形成方法，所述方法包括提供包括导电区域的衬底; 在间隔物的上部形成具有部分暴露的侧壁区域的间隔物，其限定相变存储元件接触区域; 并且其中所述间隔件底部部分与所述导电区域重叠。 这两种方法都可以减少相变存储元件的有效面积，从而减少所需的相变电流。

公开(公告)号：US20080239794A1

公开(公告)日：2008-10-02

申请号：US11840051

申请日：2007-08-16

Applicant: Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

Inventor： Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

IPC: G11C11/00

CPC classification number: G11C11/16

Abstract: Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.

Abstract translation: 这里公开了具有小角度切换写入线的触发模式磁阻随机存取存储器（MRAM）器件以及触发模式切换MRAM器件的相关方法。 还公开了根据所公开的原理构造的MRAM装置的布局。 一般来说，所公开的原理提供用于切换切换模式MRAM器件的非正交对准的触发模式写入线，其使用偏置场来降低切换每个器件的磁状态所需的阈值。 虽然常规的切换模式写入线提供所施加的磁场的期望的正交取向以优化器件切换，但偏置场的使用影响该正交取向。 如本文所公开的，通过非正交对准这两个写入线，可以补偿偏置场的有害影响，使得如所期望的那样，施加到两条线的器件的净场也基本正交。