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31.发明申请公开(公告)号：US20200249744A1
公开(公告)日：2020-08-06
申请号：US16780734
申请日：2020-02-03
Applicant: Apple Inc.
Inventor： Karan Sanghi , Saurabh Garg , Haining Zhang
IPC: G06F1/3293 , G06F11/14 , G06F9/4401 , G06F1/3234 , G06F1/3228 , G06F13/42 , G06F1/3287
Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
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公开(公告)号：US20200218326A1
公开(公告)日：2020-07-09
申请号：US16820307
申请日：2020-03-16
Applicant: Apple Inc.
Inventor： Saurabh Garg , Karan Sanghi , Vladislav Petkov , Richard Solotke
IPC: G06F1/3234 , G06F13/40 , G06F13/42 , G06F1/3203 , G06F1/3287 , G06F9/30 , G06F9/4401
Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.
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33.发明申请公开(公告)号：US20200174953A1
公开(公告)日：2020-06-04
申请号：US16780743
申请日：2020-02-03
Applicant: Apple Inc.
Inventor： Karan Sanghi , Vladislav Petkov , Radha Kumar Pulyala , Saurabh Garg , Haining Zhang
Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
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公开(公告)号：US10430352B1
公开(公告)日：2019-10-01
申请号：US15984153
申请日：2018-05-18
Applicant: Apple Inc.
Inventor： Karan Sanghi , Saurabh Garg , Vladislav V. Petkov
IPC: G06F13/16 , G06F12/0831 , G06F15/167 , G06F15/173
Abstract: Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).
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公开(公告)号：US10372637B2
公开(公告)日：2019-08-06
申请号：US15721485
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Radha Kumar Pulyala , Saurabh Garg , Karan Sanghi
Abstract: Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.
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Patent Agency Ranking
公开(公告)号：US10331612B1
公开(公告)日：2019-06-25
申请号：US15865638
申请日：2018-01-09
Applicant: Apple Inc.
Inventor： Vladislav Petkov , Saurabh Garg , Karan Sanghi , Haining Zhang
CPC classification number: G06F15/17 , G06F13/4221 , H04W4/80
Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.
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37.发明申请公开(公告)号：US20190086993A1
公开(公告)日：2019-03-21
申请号：US16133543
申请日：2018-09-17
Applicant: Apple Inc.
Inventor： Karan Sanghi , Saurabh Garg , Haining Zhang
Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
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38.发明申请公开(公告)号：US20190042525A1
公开(公告)日：2019-02-07
申请号：US15720603
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Jason McElrath , Karan Sanghi , Saurabh Garg
CPC classification number: G06F13/4291 , G06F9/466 , G06F9/546 , G06F13/1673 , G06F13/3625 , H04L25/00 , H04W72/12 , H04W84/042
Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.
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39.发明申请公开(公告)号：US20180292885A1
公开(公告)日：2018-10-11
申请号：US15942230
申请日：2018-03-30
Applicant: APPLE INC.
Inventor： Karan Sanghi , Saurabh Garg , Haining Zhang
CPC classification number: G06F1/3293 , G06F1/3228 , G06F1/3243 , G06F1/3287 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F11/1417 , G06F11/1471 , G06F11/1474 , G06F13/4282 , G06F2201/805 , G06F2201/87 , Y02D10/122 , Y02D10/14 , Y02D10/151 , Y02D10/152 , Y02D10/171
Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
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公开(公告)号：US09971397B2
公开(公告)日：2018-05-15
申请号：US14879027
申请日：2015-10-08
Applicant: Apple Inc.
Inventor： Karan Sanghi , Saurabh Garg , Haining Zhang
CPC classification number: G06F1/3293 , G06F1/3228 , G06F1/3243 , G06F1/3287 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F11/1417 , G06F11/1471 , G06F11/1474 , G06F13/4282 , G06F2201/805 , G06F2201/87 , Y02D10/122 , Y02D10/14 , Y02D10/151 , Y02D10/152 , Y02D10/171
Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
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