公开(公告)号：US20200279067A1

公开(公告)日：2020-09-03

申请号：US16877400

申请日：2020-05-18

Applicant: Arm Limited

Inventor： Divya Madapusi Srinivas Prasad ,  Saurabh Pijuskumar Sinha ,  Brian Tracy Cline ,  Stephen Lewis Moore

IPC: G06F30/394 ,  G06F30/392

Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.

公开(公告)号：US10741246B2

公开(公告)日：2020-08-11

申请号：US15960365

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Brian Tracy Cline ,  George McNeil Lattimore ,  Bal S. Sandhu

IPC: G11C11/00 ,  G11C14/00 ,  G11C7/06 ,  G11C13/00

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

公开(公告)号：US20200218845A1

公开(公告)日：2020-07-09

申请号：US16820471

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

IPC: G06F30/392 ,  H01L27/02 ,  H01L23/522

Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized or legal locations.

公开(公告)号：US10607659B2

公开(公告)日：2020-03-31

申请号：US15960405

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Shidhartha Das ,  George McNeil Lattimore ,  Brian Tracy Cline

IPC: G11C5/06 ,  G11C14/00 ,  G11C8/10 ,  G11C13/00

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

公开(公告)号：US10083269B2

公开(公告)日：2018-09-25

申请号：US14528314

申请日：2014-10-30

Applicant: ARM Limited

Inventor： Paul De Dood ,  Marlin Wayne Frederick ,  Jerry Chaoyuan Wang ,  Brian Douglas Ngai Lee ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Yanbin Jiang ,  Emmanuel Jean Marie Olivier Pacaud ,  Matthieu Domonique Henri Pauly ,  Sylvia Xiuhui Li ,  Thanusree Achuthan ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

公开(公告)号：US09929149B2

公开(公告)日：2018-03-27

申请号：US15188544

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Robert Campbell Aitken ,  Brian Tracy Cline ,  Gregory Munson Yeric ,  Kyungwook Chang

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/73207

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

公开(公告)号：US09638752B2

公开(公告)日：2017-05-02

申请号：US14175015

申请日：2014-02-07

Applicant: ARM LIMITED ,  THE REGENTS OF THE UNIVERSITY OF MICHIGAN

Inventor： Yejoong Kim ,  Dennis Michael Sylvester ,  David Theodore Blaauw ,  Brian Tracy Cline

IPC: G06F19/00 ,  G01R31/317 ,  H03K3/03

CPC classification number: G01R31/31725 ,  H03K3/0315

Abstract: A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period. A reference ring oscillator has a plurality of reference unit cells arranged to form a reference ring, and generates a second output signal having a second oscillation period, each reference unit cell comprising components configured such that the second oscillation period provides an indication of a propagation delay through the pulse generation circuitry of the main unit cells of the main ring during the first oscillation period. Calculation circuitry then determines the clock node to output node delay of the flip-flop from the first oscillation period and the second oscillation period. This provides a particularly simple and accurate mechanism for calculating the clock node to output node delay of a flip-flop.