公开(公告)号：US11119961B2

公开(公告)日：2021-09-14

申请号：US16655403

申请日：2019-10-17

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Dimitrios Kaseridis

IPC: G06F13/00 ,  G06F13/40 ,  G06F12/0811 ,  G06F12/0817 ,  G06F13/16

Abstract: A method and apparatus for data transfer in a data processing network uses both ordered and optimized write requests. A first write request is received at a first node of the data processing network is directed to a first address and has a first stream identifier. The first node determines if any previous write request with the same first stream identifier is pending. When a previous write request is pending, a request for an ordered write is sent to a Home Node of the data processing network associated with the first address. When no previous write request to the first stream identifier is pending, a request for an optimized write is sent to the Home Node. The Home Node and first node are configured to complete a sequence of ordered write requests before the associated data is made available to other elements of the data processing network.

公开(公告)号：US11055250B2

公开(公告)日：2021-07-06

申请号：US16593127

申请日：2019-10-04

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Klas Magnus Bruce ,  Damien Guillaume Pierre Payet ,  Jamshed Jalal ,  Alex James Waugh

IPC: G06F13/40 ,  G06F12/0815 ,  G06F13/16

Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.

公开(公告)号：US10761987B2

公开(公告)日：2020-09-01

申请号：US16202171

申请日：2018-11-28

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Mark David Werkheiser ,  Michael Filippo ,  Klas Magnus Bruce ,  Paul Gilbert Meyer

IPC: G06F12/0815 ,  G06F13/16

Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units. The coherent interconnect may receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data. The coherent interconnect is arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed. In that event, a pass condition is identified for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.

公开(公告)号：US10713187B2

公开(公告)日：2020-07-14

申请号：US16521621

申请日：2019-07-25

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Paul Gilbert Meyer ,  David Joseph Hawkins ,  Phanindra Kumar Mannava ,  Joseph Michael Pusdesris

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0831 ,  G06F12/0844

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

公开(公告)号：US10657055B1

公开(公告)日：2020-05-19

申请号：US16218962

申请日：2018-12-13

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Mark David Werkheiser ,  Gurunath Ramagiri ,  Mukesh Patel

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0804 ,  G06F12/0817

Abstract: An apparatus and method are provided for managing snoop operations. The apparatus has an interface for receiving access requests from any of N master devices that have associated cache storage, each access request specifying a memory address within memory associated with the apparatus. Snoop filter storage is provided that has a plurality of snoop filter entries, where each snoop filter entry identifies a memory portion and snoop control information indicative of the master devices that have accessed that memory portion. When an access request received at the interface specifies a memory address that is within the memory portion associated with a snoop filter entry, snoop control circuitry uses the snoop control information in that snoop filter entry to determine which master devices to subject to a snoop operation. The snoop control circuitry maintains master indication data used to identify a first subset of the plurality of master devices whose accesses to the memory are to be precisely tracked within the snoop filter storage. The first subset comprises up to M master devices, where M is less than N. Each snoop filter entry has a precise tracking field and an imprecise tracking field. When multiple master devices have accessed the memory portion associated with a snoop filter entry, then the precise tracking field is used to precisely identify each master device of those multiple master devices that is within the first subset. When the multiple master devices includes at least one master device that is not in the first subset, then a generic indication is set in the imprecise tracking field.

公开(公告)号：US10157133B2

公开(公告)日：2018-12-18

申请号：US14965131

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Jamshed Jalal ,  Mark David Werkheiser

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0831

Abstract: A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.

公开(公告)号：US09900260B2

公开(公告)日：2018-02-20

申请号：US14965237

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Ramamoorthy Guru Prasadh ,  Jamshed Jalal ,  Ashok Kumar Tummala ,  Phanindra Kumar Mannava ,  Tushar P. Ringe

IPC: H04L12/891 ,  H04L12/26 ,  H04L12/835 ,  H04L29/06

CPC classification number: H04L47/41 ,  H04L43/106 ,  H04L43/16 ,  H04L47/30 ,  H04L69/08 ,  H04L69/18 ,  H04L69/22

Abstract: A bridging circuit and method of operation thereof, which couples first and second electronic circuits of a data processing system. The first electronic circuit generates signals corresponding to digits of a flow control unit (flit) of a first flow control protocol and where the second electronic circuit is responsive to signals corresponding to flits of a second flow control protocol. When first flits are destined for the same target buffer, they are combined to provide a second flit consistent with the second flow control protocol and transmitting the second flit to the second electronic circuit. The second flit includes data and metadata fields copied from the first flits, a common field common to each of the first flits, a merged field containing a merger of fields from the first flits and a validity field indicating which portions of the second flit contain valid data.

公开(公告)号：US12079132B2

公开(公告)日：2024-09-03

申请号：US18101806

申请日：2023-01-26

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Ashok Kumar Tummala ,  Wenxuan Zhang ,  Daniel Thomas Pinero ,  Tushar P Ringe

IPC: G06F12/00 ,  G06F12/0888

CPC classification number: G06F12/0888 ,  G06F2212/1024

Abstract: Data transfer between caching domains of a data processing system is achieved by a local coherency node (LCN) of a first caching domain receiving a read request for data associated with a second caching domain, from a requesting node of the first caching domain. The LCN requests the data from the second caching domain via a transfer agent. In response to receiving a cache line containing the data from the second caching domain, the transfer agent sends the cache line to the requesting node, bypassing the LCN and, optionally, sends a read-receipt indicating the state of the cache line to the LCN. The LCN updates a coherency state for the cache line in response to receiving the read-receipt from the transfer agent and a completion acknowledgement from the requesting node. Optionally, the transfer agent may send the cache line via the LCN when congestion is detected in a response channel of the data processing system.

公开(公告)号：US20240273025A1

公开(公告)日：2024-08-15

申请号：US18109453

申请日：2023-02-14

Applicant: Arm Limited

Inventor： Wenxuan Zhang ,  Jamshed Jalal ,  Mark David Werkheiser ,  Sakshi Verma ,  Ritukar Khanna ,  Devi Sravanthi Yalamarthy ,  Gurunath Ramagiri ,  Mukesh Patel ,  Tushar P Ringe

IPC: G06F12/0831 ,  G06F12/0871

CPC classification number: G06F12/0833 ,  G06F12/0871

Abstract: A super home node of a first chip of a multi-chip data processing system manages coherence for both local and remote cache lines accessed by local caching agents and local cache lines accessed by caching agents of one or more second chips. Both local and remote cache lines are stored in a shared cache, and requests are stored in shared point-of-coherency queue. An entry in a snoop filter table of the super home node includes a presence vector that indicates the presence of a remote cache line at specific caching agents of the first chip or the presence of a local cache line at specific caching agents of the first chip and any caching agent of the second chip. All caching agents of the second chip are represented as a single caching agent in the presence vector.

公开(公告)号：US11599467B2

公开(公告)日：2023-03-07

申请号：US17331806

申请日：2021-05-27

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Bruce James Mathewson ,  Tushar P Ringe ,  Sean James Salisbury ,  Antony John Harris

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0895

Abstract: The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.