公开(公告)号：US12117935B2

公开(公告)日：2024-10-15

申请号：US17852300

申请日：2022-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Benjamin Tsien ,  Alexander J. Branover

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60 ,  G06F13/00 ,  H10B10/00 ,  H10B12/00

Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

公开(公告)号：US20230090126A1

公开(公告)日：2023-03-23

申请号：US17483694

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Thomas J. Gibney ,  Jose G. Cruz ,  Pravesh Gupta ,  Chintan S. Patel

IPC: G06F1/3234 ,  G06F11/14 ,  G06F3/06

Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

公开(公告)号：US11580025B1

公开(公告)日：2023-02-14

申请号：US17490529

申请日：2021-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tarun Nakra ,  Akhil Arunkumar ,  Vydhyanathan Kalyanasundharam ,  Chintan S. Patel ,  Nithesh Kurella Lakshmi Narayanamurthy

IPC: G06F12/0862

Abstract: Systems and methods for coordinated memory-side cache prefetching and dynamic interleaving configuration modification involve modifying one or both of the prefetch distance or the prefetch degree used by prefetcher modules of one or more memory-side caches by modifying interleaving configuration data following detection of an interleaving reconfiguration trigger condition indicative, for example, of low prefetch accuracy, low prefetch coverage, high prefetch lateness, or a combination of these. In response an interleaving reconfiguration trigger condition, a processor modifies the interleaving configuration data for the processing system based on the prefetch performance characteristics associated with the interleaving reconfiguration trigger condition. In some embodiments, the interleaving configuration data is modified by changing which physical memory address indices are used to determine the bits that define the channel identification number to which that physical memory address is to be mapped.

公开(公告)号：US20210090613A1

公开(公告)日：2021-03-25

申请号：US17113322

申请日：2020-12-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Alan Dodson Smith ,  Chintan S. Patel

IPC: G11C5/06 ,  G06F1/3296 ,  G06F13/40 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3287 ,  G11C5/02 ,  G11C5/14

Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.

公开(公告)号：US10601723B2

公开(公告)日：2020-03-24

申请号：US15951844

申请日：2018-04-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Vydhyanathan Kalyanasundharam ,  Bryan P. Broussard ,  Greggory D. Donley ,  Chintan S. Patel

IPC: H04L12/873 ,  H04L12/841 ,  H04L12/877 ,  H04L12/875 ,  H04L12/54 ,  H04L12/70

Abstract: A computing system uses a memory for storing data, one or more clients for generating network traffic and a communication fabric with network switches. The network switches include centralized storage structures, rather than separate input and output storage structures. The network switches store particular metadata corresponding to received packets in a single, centralized collapsing queue where the age of the packets corresponds to a queue entry position. The payload data of the packets are stored in a separate memory, so the relatively large amount of data is not shifted during the lifetime of the packet in the network switch. The network switches select sparse queue entries in the collapsible queue, deallocate the selected queue entries, and shift remaining allocated queue entries toward a first end of the queue with a delay proportional to the radix of the network switches.

公开(公告)号：US10372414B2

公开(公告)日：2019-08-06

申请号：US15796521

申请日：2017-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Alan Dodson Smith

IPC: G06F7/535 ,  G06F7/498 ,  G06F16/901

Abstract: Systems, apparatuses, and methods for implementing a fractional pointer lookup table are disclosed. A system includes a fractional pointer lookup table and control logic coupled to the table. The control logic performs an access to the table with a numerator and a denominator, wherein the numerator and the denominator are integers. The control logic receives a result of the lookup, wherein the result is either a rounded-up value of a quotient of the numerator and denominator or a rounded-down value of the quotient. In one embodiment, the control logic provides a fractional pointer to the table with each access and receives a fractional pointer limit from the table. The control logic initializes the fractional pointer to zero, increments the fractional pointer after each access to the table, and resets the fractional pointer to zero when the fractional pointer reaches the fractional pointer limit.

公开(公告)号：US20190140954A1

公开(公告)日：2019-05-09

申请号：US15805762

申请日：2017-11-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Chintan S. Patel ,  Eric Christopher Morton ,  Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: H04L12/803 ,  H04L12/935 ,  H04L12/825

Abstract: A system for implementing load balancing schemes includes one or more processing units, a memory, and a communication fabric with a plurality of switches coupled to the processing unit(s) and the memory. A switch of the fabric determines a first number of streams on a first input port that are targeting a first output port. The switch also determines a second number of requestors, from all input ports, that are targeting the first output port. Then, the switch calculates a throttle factor for the first input port by dividing the first number of streams by the second number of streams. The switch applies the throttle factor to regulate bandwidth on the first input port for requestors targeting the first output port. The switch also calculates throttle factors for the other ports and applies the throttle factors when regulating bandwidth on the other ports.

公开(公告)号：US20190108861A1

公开(公告)日：2019-04-11

申请号：US15725912

申请日：2017-10-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Alan Dodson Smith ,  Chintan S. Patel

IPC: G11C5/06 ,  G11C5/02 ,  G11C5/14

Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.