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    Memory systems and methods of operating the memory systems
    31.
    发明申请
    Memory systems and methods of operating the memory systems 有权
    内存系统和操作内存系统的方法

    公开(公告)号：US20080082762A1

    公开(公告)日：2008-04-03

    申请号：US11529711

    申请日：2006-09-28

    申请人： Andreas Taeuber ,  Detlev Richter ,  Luca de Ambroggi ,  Rainer Spielberg

    发明人： Andreas Taeuber ,  Detlev Richter ,  Luca de Ambroggi ,  Rainer Spielberg

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4239

    摘要： In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.

    摘要翻译： 在本发明的一个实施例中，提供了一种操作存储器系统的方法，包括同时从存储器系统的多个存储器读取数据，并以存储器系统的I / O端口的输出通道容量从存储器系统输出数据 所述存储器系统通过将从所述多个存储器中的至少一些存储器读取的数据的数据总线宽度转换为所述I / O端口的数据总线宽度。

    Semiconductor module with a configuration for the self-test of a plurality of interface circuits and test method
    32.
    发明授权
    Semiconductor module with a configuration for the self-test of a plurality of interface circuits and test method 有权
    具有用于多个接口电路的自检的配置的半导体模块和测试方法

    公开(公告)号：US07296202B2

    公开(公告)日：2007-11-13

    申请号：US10075656

    申请日：2002-02-13

    申请人： Detlev Richter

    发明人： Detlev Richter

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3185 ,  G01R31/3187 ,  G06F2201/83

    摘要： A semiconductor module with a plurality of interface circuits has a configuration for the self-test of interface circuits, with two equally sized groups of interface circuits such that each interface circuit of the first group is assigned exactly one interface circuit of the second group. A circuit interacts with the first group and serves for generating test signals which can be output via the interface circuits of the first group. Another circuit interacts with the second group and serves for receiving and processing test signals received via the interface circuits of the second group, so that a connection of the assigned interface circuits of the first and second groups enables a self-test, the first and second groups of interface circuits having a separate voltage supply. This enables good test coverage by separate variation of the voltage of transmitting and receiving group.

    摘要翻译： 具有多个接口电路的半导体模块具有用于接口电路的自检的配置，具有两个相同大小的接口电路组，使得第一组的每个接口电路被精确地分配给第二组的一个接口电路。 电路与第一组相互作用，用于产生可通过第一组的接口电路输出的测试信号。 另一个电路与第二组相互作用并且用于接收和处理经由第二组的接口电路接收的测试信号，使得第一和第二组的分配的接口电路的连接能够进行自检，第一和第二组 具有单独电压源的接口电路组。 这样可以通过发送和接收组的电压的单独变化实现良好的测试覆盖。

    Circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit
    33.
    发明授权
    Circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit 有权
    具有温度依赖性半导体元件测试和修复逻辑电路的电路配置

    公开(公告)号：US06297995B1

    公开(公告)日：2001-10-02

    申请号：US09440721

    申请日：1999-11-15

    申请人： Roderick Mc Connell ,  Detlev Richter

    发明人： Roderick Mc Connell ,  Detlev Richter

    IPC分类号： G11C1122

    CPC分类号： G01R31/30

    摘要： A circuit configuration with a temperature-dependent semiconductor component self-test and repair logic circuit, in which at least one temperature sensor is provided in a semiconductor chip having a semiconductor component. In addition, the semiconductor component is connected in the semiconductor chip with the self-test and repair logic circuit.

    摘要翻译： 具有温度依赖性半导体部件自检和修复逻辑电路的电路配置，其中在具有半导体部件的半导体芯片中提供至少一个温度传感器。 此外，半导体元件与半导体芯片中的自检和修复逻辑电路连接。

    Configuration of memory cells and method of checking the operation of memory cells
    34.
    发明授权
    Configuration of memory cells and method of checking the operation of memory cells 有权
    存储单元的配置以及检查存储单元操作的方法

    公开(公告)号：US06279129B1

    公开(公告)日：2001-08-21

    申请号：US09465726

    申请日：1999-12-17

    申请人： Roderick McConnell ,  Detlev Richter

    发明人： Roderick McConnell ,  Detlev Richter

    IPC分类号： G11C2900

    CPC分类号： G11C29/44 ,  G11C2029/1208

    摘要： A method of checking the operation of memory cells. A first group of memory cells and a second group of memory cells are provided. The first group of memory cells is tested and a first set of test results is obtained, and the first set of test results is stored in the second group of memory cells. The first set of test results is read from the second group of memory cells. The second group of memory cells is tested and a second set of test results is obtained. The second set of test results is stored in the first group of memory cells. The test results can be compressed before they are output. Errors can be corrected by using an error correction code or duplicate copies of the test results. The method allows a test device to be provided that does not have memory. The complexity of the test device is therefore advantageously reduced. An electronic circuit is provided that includes a first group of memory cells, a second group of memory cells, and a test device programmed such that the method can be performed.

    摘要翻译： 检查存储单元的操作的方法。 提供了第一组存储器单元和第二组存储单元。 测试第一组存储器单元并且获得第一组测试结果，并且将第一组测试结果存储在第二组存储器单元中。 从第二组存储单元读取第一组测试结果。 测试第二组记忆单元，并获得第二组测试结果。 第二组测试结果存储在第一组存储单元中。 测试结果可以在输出之前进行压缩。 可以通过使用纠错码或测试结果的副本来纠正错误。 该方法允许提供没有存储器的测试设备。 因此有利地减少了测试装置的复杂性。 提供一种电子电路，其包括第一组存储器单元，第二组存储器单元和被编程的测试装置，使得可以执行该方法。

    X-Ray generator incorporating automatic correction of a dose-determining exposure parameter
    35.
    发明授权
    X-Ray generator incorporating automatic correction of a dose-determining exposure parameter 失效
    其包括剂量确定曝光参数的自动校正的X射线发生器

    公开(公告)号：US4486896A

    公开(公告)日：1984-12-04

    申请号：US406602

    申请日：1982-08-09

    申请人： Detlev Richter ,  Thomas Burrig

    发明人： Detlev Richter ,  Thomas Burrig

    IPC分类号： H05G1/46 ,  H05G1/36 ,  H05G1/44 ,  H05G1/30

    CPC分类号： H05G1/44

    摘要： The density of an X-ray exposure depends not only on the exposure parameters, but also on the film development parameters. In order to eliminate the effect of fluctuations in the latter parameters, the X-ray generator in accordance with the invention comprises a measuring device which measures the density of a test exposure and which acts on an adjusting member for the exposure parameters. By subjecting the test exposure to the same conditions as the X-ray exposure, the effects of parameter fluctuations during film processing process can be eliminated to a high degree.

    摘要翻译： X射线曝光的密度不仅取决于曝光参数，还取决于胶片显影参数。 为了消除后一参数的波动的影响，根据本发明的X射线发生器包括测量测试曝光的密度并作用于调节构件以用于曝光参数的测量装置。 通过使测试曝光与X射线曝光相同的条件，可以高度地消除胶片处理过程中的参数波动的影响。

    Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation
    36.
    发明授权
    Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation 有权
    在访问操作中使用多个缓冲电路来操作该集成电路的集成电路和方法

    公开(公告)号：US07920430B2

    公开(公告)日：2011-04-05

    申请号：US12166112

    申请日：2008-07-01

    申请人： Gert Koebernik ,  Jan Gutsche ,  Christoph Friederich ,  Detlev Richter

    发明人： Gert Koebernik ,  Jan Gutsche ,  Christoph Friederich ,  Detlev Richter

    IPC分类号： G11C7/10

    CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

    摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.

    摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括存储存储单元的多个多位信息，多个缓冲电路，每个缓冲电路耦合到多个位信息存储存储单元中的至少一个多位信息存储存储单元，以及一个 控制器，被配置为控制访问操作以使用耦合到要被访问的所述至少一个多位信息存储存储器单元的缓冲电路访问存储单元的至少一个多位信息，以及至少一个其他多位信息的缓冲电路 存储存储器单元耦合到至少一个其他多位信息存储存储单元。

    Integrated circuit having NAND memory cell strings
    37.
    发明授权
    Integrated circuit having NAND memory cell strings 有权
    具有NAND存储单元串的集成电路

    公开(公告)号：US07778073B2

    公开(公告)日：2010-08-17

    申请号：US11872655

    申请日：2007-10-15

    申请人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

    发明人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/11568

    摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

    摘要翻译： 本发明的实施例一般涉及用于制造集成电路的集成电路和方法。 在本发明的实施例中，提供了具有存储单元的集成电路。 存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区 旁边的沟槽。

    SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY COMPRISING A PLURALITY OF MEMORY CELLS
    39.
    发明申请
    SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY COMPRISING A PLURALITY OF MEMORY CELLS 有权
    用于操作包含大量存储器单元的半导体存储器的半导体存储器和方法

    公开(公告)号：US20070076462A1

    公开(公告)日：2007-04-05

    申请号：US11240659

    申请日：2005-09-30

    申请人： Detlev Richter ,  Konrad Seidel

    发明人： Detlev Richter ,  Konrad Seidel

    IPC分类号： G11C17/00

    CPC分类号： G11C16/3418

    摘要： A method for operating a semiconductor memory (M) comprising a plurality of memory cells (MC), wherein the memory cells (MC) are arranged adjacent to one another, the arrangement starts with a first memory cell (MF) and ends with a last memory cell (ML), each memory cell (MC) has a first side (S) and a second side (D), the memory cells (MC) are connected by a bitline (BL) on the first side (S) of the memory cell and connected by another bitline (BL) on the second side (D) of the memory cell, the first side (S) of a memory cell is connected to a same bitline (BL) as the second side (D) of an adjacent memory cell, each of the memory cells (MC) is connected by a same wordline (WL), comprising the steps of: selecting a memory cell (MC) for operation, applying a first potential (VS) to all the bitlines (BL) connected to memory cells (MC) arranged to the first side (S) of the memory cell, applying a second potential (VD) to all the bitlines (BL) connected to memory cells (MC) arranged to the second side (D) of the memory cell, and performing the desired operation on the memory cell (MC).

    摘要翻译： 一种用于操作包括多个存储单元（MC）的半导体存储器（M）的方法，其中所述存储单元（MC）彼此相邻布置，所述布置从第一存储单元（MF）开始并以最后一个结束 存储单元（ML），每个存储单元（MC）具有第一侧（S）和第二侧（D），存储单元（MC）通过位线（S）的第一侧（S）上的位线 存储单元并且通过存储单元的第二侧（D）上的另一位线（BL）连接，存储单元的第一侧（S）连接到与第一侧（D）相同的位线（BL） 每个存储单元（MC）通过相同的字线（WL）连接，包括以下步骤：选择用于操作的存储单元（MC），将第一电位（VS）应用于所有位线（BL ）连接到被布置到存储器单元的第一侧（S）的存储器单元（MC），向连接到布置到存储器单元（MC）的存储器单元（MC）的所有位线施加第二电位（VD） 存储单元的第二侧（D），并对存储单元（MC）执行所需的操作。