Circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit
    1.
    发明授权
    Circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit 有权
    具有温度依赖性半导体元件测试和修复逻辑电路的电路配置

    公开(公告)号:US06297995B1

    公开(公告)日:2001-10-02

    申请号:US09440721

    申请日:1999-11-15

    IPC分类号: G11C1122

    CPC分类号: G01R31/30

    摘要: A circuit configuration with a temperature-dependent semiconductor component self-test and repair logic circuit, in which at least one temperature sensor is provided in a semiconductor chip having a semiconductor component. In addition, the semiconductor component is connected in the semiconductor chip with the self-test and repair logic circuit.

    摘要翻译: 具有温度依赖性半导体部件自检和修复逻辑电路的电路配置,其中在具有半导体部件的半导体芯片中提供至少一个温度传感器。 此外,半导体元件与半导体芯片中的自检和修复逻辑电路连接。

    Integrated memory
    2.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号:US06216248B1

    公开(公告)日:2001-04-10

    申请号:US09243296

    申请日:1999-02-02

    IPC分类号: H03M1300

    摘要: An integrated memory has a first and a second mode of operation as well as a first memory area and a second memory area. The first memory area is used to store useful data in both modes of operation. The second memory area is used in the first, but not in the second, mode of operation to store error correction data for the useful data which are to be stored in the first memory area. In the first mode of operation, the memory thus has an error correction function that is deactivated during the second mode of operation.

    摘要翻译: 集成存储器具有第一和第二操作模式以及第一存储器区域和第二存储器区域。 第一个存储区用于在两种操作模式下存储有用的数据。 在第一存储区域中使用第二存储区域,而不是在第二存储器模式中存储要存储在第一存储器区域中的有用数据的纠错数据。 在第一操作模式中,存储器具有在第二操作模式期间停用的纠错功能。

    Integrated Circuit Having NAND Memory Cell Strings
    7.
    发明申请
    Integrated Circuit Having NAND Memory Cell Strings 有权
    具有NAND存储器单元串的集成电路

    公开(公告)号:US20090097317A1

    公开(公告)日:2009-04-16

    申请号:US11872655

    申请日:2007-10-15

    摘要: Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

    摘要翻译: 本发明的实施例一般涉及用于制造集成电路的集成电路和方法。 在本发明的实施例中,提供了具有存储单元的集成电路。 存储单元可以包括载体中的沟槽,沟槽中的电荷俘获层结构,电荷俘获层结构包括至少两个分离的电荷俘获区,至少部分填充在沟槽中的导电材料以及源/漏区 旁边的沟槽。

    Automatic exposure control device for an X-ray generator
    8.
    发明授权
    Automatic exposure control device for an X-ray generator 失效
    用于X射线发生器的自动曝光控制装置

    公开(公告)号:US4313055A

    公开(公告)日:1982-01-26

    申请号:US47559

    申请日:1979-06-08

    IPC分类号: H05G1/44 H05G1/42

    CPC分类号: H05G1/44

    摘要: The automatic exposure control devices of contemporary X-ray generators have a constant lead time which accurately takes into account the actual ratios or delays only for a given setting of current and voltage. Particularly in the case of high voltages and small currents, the lead times are too short, thus giving rise to overexposures. The invention provides an automatic exposure control device in which the lead time is calculated from the exposure data by an arithmetic unit. The lead time is adjusted on a correspondingly constructed adjustable lead time network. An arithmetic unit of this kind is not required for the programmed exposure technique. The correct lead times can then be programmed and stored together with the other exposure parameters.

    摘要翻译: 现代X射线发生器的自动曝光控制装置具有恒定的提前时间,仅在给定的电流和电压设置下才能精确地考虑实际比例或延迟。 特别是在高电压和小电流的情况下,导通时间太短,从而导致过度曝光。 本发明提供了一种自动曝光控制装置,其中通过运算单元根据曝光数据计算提前时间。 在相应构建的可调节前置时间网络上调整前置时间。 编程曝光技术不需要这种算术单元。 然后可以将正确的交货时间与其他曝光参数一起编程和存储。