摘要:
A circuit configuration with a temperature-dependent semiconductor component self-test and repair logic circuit, in which at least one temperature sensor is provided in a semiconductor chip having a semiconductor component. In addition, the semiconductor component is connected in the semiconductor chip with the self-test and repair logic circuit.
摘要:
An integrated memory has a first and a second mode of operation as well as a first memory area and a second memory area. The first memory area is used to store useful data in both modes of operation. The second memory area is used in the first, but not in the second, mode of operation to store error correction data for the useful data which are to be stored in the first memory area. In the first mode of operation, the memory thus has an error correction function that is deactivated during the second mode of operation.
摘要:
A method of storing data in a memory is provided, including testing a plurality of memory cells of a plurality of memory cell sectors. Each memory cell sector includes a plurality of memory cells. Each memory cell sector is classified into at least one quality class of a plurality of quality classes depending on the results of the testing of the memory cells of the respective memory cell sector. Data is stored in the memory cells of the classified memory cell sectors depending on the quality class of the respective memory cell sector.
摘要:
Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.
摘要:
In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided.
摘要:
In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.
摘要:
Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.
摘要:
The automatic exposure control devices of contemporary X-ray generators have a constant lead time which accurately takes into account the actual ratios or delays only for a given setting of current and voltage. Particularly in the case of high voltages and small currents, the lead times are too short, thus giving rise to overexposures. The invention provides an automatic exposure control device in which the lead time is calculated from the exposure data by an arithmetic unit. The lead time is adjusted on a correspondingly constructed adjustable lead time network. An arithmetic unit of this kind is not required for the programmed exposure technique. The correct lead times can then be programmed and stored together with the other exposure parameters.
摘要:
Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation.
摘要:
In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a memory cell block having a plurality of memory cells, a storage portion configured to store information about a quality characteristic of the memory cells of the memory cell block, and a controller configured to control a read operation, and to change the information about the quality characteristic depending on a quality of a read operation.