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    Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells
    1.
    发明授权
    Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells 有权
    用于操作包括多个存储单元的半导体存储器的半导体存储器和方法

    公开(公告)号：US07190605B1

    公开(公告)日：2007-03-13

    申请号：US11240659

    申请日：2005-09-30

    申请人： Detlev Richter ,  Konrad Seidel

    发明人： Detlev Richter ,  Konrad Seidel

    IPC分类号： G11C17/00

    CPC分类号： G11C16/3418

    摘要： A method for operating a semiconductor memory (M) including a plurality of memory cells (MC), wherein the memory cells (MC) are arranged adjacent to one another, the arrangement starts with a first memory cell (MF) and ends with a last memory cell (ML), each memory cell (MC) has a first side (S) and a second side (D), the memory cells (MC) are connected by a bitline (BL) on the first side (S) of the memory cell and connected by another bitline (BL) on the second side (D) of the memory cell, the first side (S) of a memory cell is connected to a same bitline (BL) as the second side (D) of an adjacent memory cell, each of the memory cells (MC) is connected by a same wordline (WL), including the steps of: selecting a memory cell (MC) for operation, applying a first potential (VS) to all the bitlines (BL) connected to memory cells (MC) arranged to the first side (S) of the memory cell, applying a second potential (VD) to all the bitlines (BL) connected to memory cells (MC) arranged to the second side (D) of the memory cell, and performing the desired operation on the memory cell (MC).

    摘要翻译： 一种用于操作包括多个存储单元（MC）的半导体存储器（M）的方法，其中所述存储单元（MC）彼此相邻布置，所述布置从第一存储单元（MF）开始并以最后一个结束 存储单元（ML），每个存储单元（MC）具有第一侧（S）和第二侧（D），存储单元（MC）通过位线（S）的第一侧（S）上的位线 存储单元并且通过存储单元的第二侧（D）上的另一位线（BL）连接，存储单元的第一侧（S）连接到与第一侧（D）相同的位线（BL） 每个存储器单元（MC）由相同的字线（WL）连接，包括以下步骤：选择用于操作的存储单元（MC），向所有位线（BL）施加第一电位（VS） ）连接到被布置到存储器单元的第一侧（S）的存储器单元（MC），对连接到布置在存储单元（MC）的存储单元（MC）的所有位线施加第二电位（VD） （D），并且对存储单元（MC）执行所需的操作。

    Memory device with adaptive sense unit and method of reading a cell array
    2.
    发明授权
    Memory device with adaptive sense unit and method of reading a cell array 有权
    具有自适应感测单元的存储器件和读取单元阵列的方法

    公开(公告)号：US07489563B2

    公开(公告)日：2009-02-10

    申请号：US11668753

    申请日：2007-01-30

    申请人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Köbernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-André Löhr ,  Sören Irmer

    发明人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Köbernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-André Löhr ,  Sören Irmer

    IPC分类号： G11C7/00

    CPC分类号： G11C16/10 ,  G11C16/26

    摘要： A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

    摘要翻译： 提供了一种存储器件，其包括能够在至少两个状态之间切换的存储器单元，其中用于检测当前状态的检测信号的阈值取决于存储器单元的数据内容。 平行于用户数据块，包括第一状态的预定位数的主控制字被存储在单元阵列的检查部分中。 通过应用不同幅度的感测信号来读取检查部分，其中在每种情况下获得辅助控制字。 通过检查每个辅助控制字中的第一状态的位数，可以检查当前感测信号向感应窗口极限的幅度的边缘，并且感测信号幅度可以永久地适应于感测窗漂移，从而 增强存储设备的可靠性。

    Memory Device with Adaptive Sense Unit and Method of Reading a Cell Array
    4.
    发明申请
    Memory Device with Adaptive Sense Unit and Method of Reading a Cell Array 有权
    具有自适应感知单元的存储器件和读取单元阵列的方法

    公开(公告)号：US20080181012A1

    公开(公告)日：2008-07-31

    申请号：US11668753

    申请日：2007-01-30

    申请人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Kobernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-Andre Lohr ,  Soren Irmer

    发明人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Kobernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-Andre Lohr ,  Soren Irmer

    IPC分类号： G11C16/26

    CPC分类号： G11C16/10 ,  G11C16/26

    摘要： A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

    摘要翻译： 提供了一种存储器件，其包括能够在至少两个状态之间切换的存储器单元，其中用于检测当前状态的检测信号的阈值取决于存储器单元的数据内容。 平行于用户数据块，包括第一状态的预定位数的主控制字被存储在单元阵列的检查部分中。 通过应用不同幅度的感测信号来读取检查部分，其中在每种情况下获得辅助控制字。 通过检查每个辅助控制字中的第一状态的位数，可以检查当前感测信号向感应窗口极限的幅度的边缘，并且感测信号幅度可以永久地适应于感测窗漂移，从而 增强存储设备的可靠性。

    SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY COMPRISING A PLURALITY OF MEMORY CELLS
    5.
    发明申请
    SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY COMPRISING A PLURALITY OF MEMORY CELLS 有权
    用于操作包含大量存储器单元的半导体存储器的半导体存储器和方法

    公开(公告)号：US20070076462A1

    公开(公告)日：2007-04-05

    申请号：US11240659

    申请日：2005-09-30

    申请人： Detlev Richter ,  Konrad Seidel

    发明人： Detlev Richter ,  Konrad Seidel

    IPC分类号： G11C17/00

    CPC分类号： G11C16/3418

    摘要： A method for operating a semiconductor memory (M) comprising a plurality of memory cells (MC), wherein the memory cells (MC) are arranged adjacent to one another, the arrangement starts with a first memory cell (MF) and ends with a last memory cell (ML), each memory cell (MC) has a first side (S) and a second side (D), the memory cells (MC) are connected by a bitline (BL) on the first side (S) of the memory cell and connected by another bitline (BL) on the second side (D) of the memory cell, the first side (S) of a memory cell is connected to a same bitline (BL) as the second side (D) of an adjacent memory cell, each of the memory cells (MC) is connected by a same wordline (WL), comprising the steps of: selecting a memory cell (MC) for operation, applying a first potential (VS) to all the bitlines (BL) connected to memory cells (MC) arranged to the first side (S) of the memory cell, applying a second potential (VD) to all the bitlines (BL) connected to memory cells (MC) arranged to the second side (D) of the memory cell, and performing the desired operation on the memory cell (MC).

    摘要翻译： 一种用于操作包括多个存储单元（MC）的半导体存储器（M）的方法，其中所述存储单元（MC）彼此相邻布置，所述布置从第一存储单元（MF）开始并以最后一个结束 存储单元（ML），每个存储单元（MC）具有第一侧（S）和第二侧（D），存储单元（MC）通过位线（S）的第一侧（S）上的位线 存储单元并且通过存储单元的第二侧（D）上的另一位线（BL）连接，存储单元的第一侧（S）连接到与第一侧（D）相同的位线（BL） 每个存储单元（MC）通过相同的字线（WL）连接，包括以下步骤：选择用于操作的存储单元（MC），将第一电位（VS）应用于所有位线（BL ）连接到被布置到存储器单元的第一侧（S）的存储器单元（MC），向连接到布置到存储器单元（MC）的存储器单元（MC）的所有位线施加第二电位（VD） 存储单元的第二侧（D），并对存储单元（MC）执行所需的操作。