公开(公告)号：US09311246B2

公开(公告)日：2016-04-12

申请号：US12284331

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods are disclosed that comprise a cache memory for storing a copy of a portion of data stored in a system memory and a cache load circuit capable of retrieving the portion of data from the system memory. The systems and methods further comprise a status memory for identifying whether or not a region of the cache memory contains data that has been accessed from the cache memory by an external device.

公开(公告)号：US09026774B2

公开(公告)日：2015-05-05

申请号：US13560294

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F9/00 ,  G06F9/44 ,  G06F12/06

CPC classification number: G06F9/4403 ,  G06F12/0638

Abstract: A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.

Abstract translation: 一种第一装置，包括配置成从具有第一存储器空间的第二装置接收具有地址的事务的接口; 翻译器，被配置为将第一类型的接收到的事务的地址转换到第一布置的第二存储器空间，第二存储器空间不同于第一存储器空间; 以及引导逻辑，被配置为将所接收的事务的引导事务映射到所述第二存储器空间中的引导区域。

公开(公告)号：US08990540B2

公开(公告)日：2015-03-24

申请号：US13560414

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/10 ,  G06F13/16

CPC classification number: G06F13/1657 ,  G06F13/14 ,  G06F13/385

Abstract: A method may include receiving, at a first integrated circuit die, a memory transaction having an address from a second integrated circuit die. The method may further include determining, at the first integrated circuit die and based on the address, if the transaction is for the first integrated circuit die and, if so, translating the address. If transaction is for a third integrated circuit die, the transaction may be transmitted, without modification to the address, to the third integrated circuit die. The translation may be based upon a first table with each entry including a first address and a second translated address corresponding to the first address, and a second table with each entry including a first address and an indication if the transaction is to be forwarded without modification to the address.

Abstract translation: 一种方法可以包括在第一集成电路管芯处接收具有来自第二集成电路管芯的地址的存储器事务。 该方法还可以包括在第一集成电路管芯处并基于地址确定该事务是否用于第一集成电路管芯，如果是，则转换该地址。 如果交易是用于第三集成电路管芯，则可以向第三集成电路管芯传送事务，而不改变地址。 翻译可以基于第一表，其中每个条目包括对应于第一地址的第一地址和第二翻译地址，以及第二表，其中每个条目包括第一地址和指示，如果交易将被转发而不进行修改 到地址。

公开(公告)号：US08930637B2

公开(公告)日：2015-01-06

申请号：US13489920

申请日：2012-06-06

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08 ,  G06F13/16

CPC classification number: G06F12/0891 ,  G06F12/0815 ,  G06F12/0817 ,  G06F13/1663

Abstract: An arrangement includes a first part and a second part. The first part includes a memory controller for accessing a memory, at least one first cache memory and a first directory. The second part includes at least one second cache memory configured to request access to said memory. The first directory is configured to use a first coherency protocol for the at least one first cache memory and a second different coherency protocol for the at least one second memory.

Abstract translation: 一种装置包括第一部分和第二部分。 第一部分包括用于访问存储器，至少一个第一高速缓冲存储器和第一目录的存储器控​​制器。 第二部分包括被配置为请求访问所述存储器的至少一个第二高速缓存存储器。 第一目录被配置为对于至少一个第一高速缓存存储器使用第一一致性协议，以及对于至少一个第二存储器使用第二不同一致性协议。

公开(公告)号：US08629544B2

公开(公告)日：2014-01-14

申请号：US12958622

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

Inventor： Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

IPC: H01L23/02 ,  H01L29/40

CPC classification number: G11C7/10 ,  G06F13/16 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04N21/426 ,  Y02D10/14

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 提供多路复用器以将控制信号和存储器事务复用到接口上，使得所述接口的多个连接由控制信号和存储器事务共享。

公开(公告)号：US20130031312A1

公开(公告)日：2013-01-31

申请号：US13560491

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0802 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: A cache memory controller including: a pre-fetch requester configured to issue pre-fetch requests, each pre-fetch request having one of a plurality of different quality of services.

Abstract translation: 一种高速缓冲存储器控制器，包括：预取请求器，被配置为发出预取请求，每个预取请求具有多个不同服务质量中的一个。

公开(公告)号：US08060732B2

公开(公告)日：2011-11-15

申请号：US11787227

申请日：2007-04-13

Applicant: Andrew Michael Jones ,  Stuart Andrew Ryan

Inventor： Andrew Michael Jones ,  Stuart Andrew Ryan

IPC: G06F9/00

CPC classification number: G06F9/4403 ,  G06F21/575 ,  G06F2221/2105

Abstract: An integrated circuit is operable to execute boot loader code and a boot code from external memory. To provide security so that the CPU does not execute malicious codes, the circuit resets in a restricted mode in which only certain functional units may be connected. In the restricted mode the CPU is only able to fetch boot code from an external memory for transfer to an internal memory. A hash function operates on the fetched boot code to determine whether it is authentic and, if it is determined that the code is authentic the circuit is reset to an unrestricted mode to continue executing from the boot code now stored in the internal memory. Further security is provided by a watchdog timer function which resets the circuit if the boot code is not determined to be authentic within a threshold period of time.

Abstract translation: 集成电路可操作以从外部存储器执行引导加载器代码和引导代码。 为了提供安全性以使CPU不执行恶意代码，该电路在仅可以连接某些功能单元的限制模式下复位。 在限制模式下，CPU只能从外部存储器获取引导代码，以传输到内部存储器。 哈希函数对获取的引导代码进行操作以确定其是否是真实的，并且如果确定代码是可信的，则电路被重置为不受限制的模式以从现在存储在内部存储器中的引导代码继续执行。 看门狗定时器功能还提供进一步的安全性，如果在阈值时间段内引导代码未被确定为可靠的，则复位电路。

公开(公告)号：US07860252B2

公开(公告)日：2010-12-28

申请号：US11682821

申请日：2007-03-06

Applicant: Stuart Andrew Ryan ,  Andrew Michael Jones

Inventor： Stuart Andrew Ryan ,  Andrew Michael Jones

IPC: H04L9/28

CPC classification number: G06F21/51

Abstract: A system is provided in which a first circuit is protected by security features provided by a second circuit. The first circuit comprises a processor which retrieves content from a memory. Initially, the contents of the memory are authenticated using security features of the second circuit to check that the processor is accessing authenticated content. To maintain security during use, the second circuit checks that the processor is accessing content from valid regions of the memory, being those that have been authenticated, and re-checks the authenticity of the content of the valid regions of memory. The combination of checking that the processor is accessing from valid regions of the memory and authenticating the content stored in the valid regions maximizes the security of the system. If any of the checking or authentication steps fail then operation of the system is impaired. The first circuit is thus protected by security features provided by the second circuit.

Abstract translation: 提供了一种系统，其中第一电路由第二电路提供的安全特征保护。 第一电路包括从存储器检索内容的处理器。 最初，使用第二电路的安全特征对存储器的内容进行认证，以检查处理器是否访问经认证的内容。 为了在使用期间保持安全性，第二电路检查处理器是否从存储器的有效区域访问内容，即已经被认证的那些内容，并重新检查存储器的有效区域的内容的真实性。 检查处理器从存储器的有效区域访问并认证存储在有效区域中的内容的组合使得系统的安全性最大化。 如果任何检查或认证步骤失败，则系统的操作受损。 因此，第一电路由第二电路提供的安全特性来保护。

公开(公告)号：US20090132768A1

公开(公告)日：2009-05-21

申请号：US12284331

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods are disclosed that comprise a cache memory for storing a copy of a portion of data stored in a system memory and a cache load circuit capable of retrieving the portion of data from the system memory. The systems and methods further comprise a status memory for identifying whether or not a region of the cache memory contains data that has been accessed from the cache memory by an external device.

Abstract translation: 公开了包括用于存储存储在系统存储器中的数据的一部分的副本的高速缓存存储器和能够从系统存储器检索数据的部分的高速缓存加载电路的系统和方法。 系统和方法还包括状态存储器，用于识别高速缓冲存储器的区域是否包含通过外部设备从高速缓冲存储器访问过的数据。

公开(公告)号：US07047245B2

公开(公告)日：2006-05-16

申请号：US10158396

申请日：2002-05-30

Applicant: Andrew Michael Jones

Inventor： Andrew Michael Jones

IPC: G06F17/30

CPC classification number: G06F9/546 ,  G06F9/52

Abstract: A processing system which comprises means for storing a plurality of items defining a queue, pointer means having a first pointer and a second pointer associated with the beginning of said queue and a second pointer associated with the back of said queue; at least one writer for adding items to said queue; at least one reader for deleting items from said queue; and means for updating said second pointer when said at least one writer adds an item to said queue, said second pointer being updated by a swap operation.