公开(公告)号：US09059316B2

公开(公告)日：2015-06-16

申请号：US13397860

申请日：2012-02-16

申请人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

发明人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L27/32 ,  H01L29/165

CPC分类号： H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

摘要翻译： 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

公开(公告)号：US08878298B2

公开(公告)日：2014-11-04

申请号：US13346165

申请日：2012-01-09

申请人： Josephine B. Chang ,  Leland Chang ,  Renee T. Mo ,  Vijay Narayanan ,  Jeffrey W. Sleight

发明人： Josephine B. Chang ,  Leland Chang ,  Renee T. Mo ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7856 ,  H01L29/66795

摘要： Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.

摘要翻译： 提供了多阈值电压（Vt）场效应晶体管（FET）器件及其制造技术。 一方面，提供一种FET器件，其包括源极区域; 漏区; 将源极和漏极区互连的至少一个沟道; 以及围绕通道的至少一部分的栅极，其被配置为具有多个阈值电压，这是由于至少一个带边缘金属选择性地放置在整个栅极上。

公开(公告)号：US08216907B2

公开(公告)日：2012-07-10

申请号：US12880478

申请日：2010-09-13

申请人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

发明人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L21/8238 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

摘要翻译： 一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层; 选择性地仅去除第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。

公开(公告)号：US08138041B2

公开(公告)日：2012-03-20

申请号：US12137745

申请日：2008-06-12

申请人： Michael P. Chudzik ,  Troy Graves-Abe ,  Rashmi Jha ,  Renee T. Mo ,  Keith Kwong Hon Wong

发明人： Michael P. Chudzik ,  Troy Graves-Abe ,  Rashmi Jha ,  Renee T. Mo ,  Keith Kwong Hon Wong

IPC分类号： H01L21/203

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/324 ,  H01L29/517

摘要： Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature. A metal layer is then deposited, and then an in-situ Si cap is deposited thereon. The Si cap is deposited without vacuum break, i.e., in the same mainframe or in the same chamber, as the heating, cooling and metal deposition processes. As such, the amount of oxygen available for interlayer oxide regrowth during subsequent processing is reduced as well as the amount oxygen trapped in the metal gate.

摘要翻译： 公开了通过沉积原位硅（Si）帽来改善金属栅极器件的性能的结构和方法。 将包括基板和电介质层的晶片通过脱气加热，然后冷却至约室温。 然后沉积金属层，然后在其上沉积原位Si盖。 在加热，冷却和金属沉积过程中，Si盖被沉积成没有真空断裂，即在相同的主框架或相同的室中。 因此，在随后的处理期间可用于层间氧化物再生长的氧气量以及金属栅极中捕获的氧量减少。

公开(公告)号：US07943460B2

公开(公告)日：2011-05-17

申请号：US12426457

申请日：2009-04-20

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US07871869B2

公开(公告)日：2011-01-18

申请号：US12543679

申请日：2009-08-19

申请人： Eduard A. Cartier ,  Steven J. Koester ,  Kingsuk Maitra ,  Amlan Majumdar ,  Renee T. Mo

发明人： Eduard A. Cartier ,  Steven J. Koester ,  Kingsuk Maitra ,  Amlan Majumdar ,  Renee T. Mo

IPC分类号： H01L21/00

CPC分类号： H01L29/6659 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78696

摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.

摘要翻译： 提供了一种极薄的绝缘体上硅晶体管，其包括衬底上的掩埋氧化物层，掩埋氧化物层上方的硅层，硅层上的栅极堆叠，硅层上的氮化物衬垫， 栅堆叠，氮化物衬垫上并与其相邻的氧化物衬垫，以及升高的源/漏区。 栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。 凸起的源极/漏极区域中的每一个具有包括硅层的一部分的第一部分，与氧化物衬垫和氮化物衬垫的部分相邻的第二部分，以及在第二部分上方的第三部分。 还提供了制造极薄的绝缘体上硅晶体管的方法。

公开(公告)号：US20100006956A1

公开(公告)日：2010-01-14

申请号：US12539842

申请日：2009-08-12

申请人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

IPC分类号： H01L29/78

CPC分类号： H01L29/517 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

摘要： A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.

摘要翻译： 公开了一种降低金属高介电常数（MHK）晶体管中的寄生电容的方法。 该方法包括在衬底上形成MHK栅极堆叠，MHK栅极堆叠层具有高介电常数材料的底层，中间金属层和非晶硅或多晶硅之一的顶层。 该方法进一步在MHK栅极堆叠的侧壁上形成耗尽的侧壁层，以覆盖中间层和顶层而不是底层。 耗尽的侧壁层是非晶硅或多晶硅之一。 该方法还在耗尽的侧壁层上方和底层的暴露表面之上形成偏移间隔层。

公开(公告)号：US20090311836A1

公开(公告)日：2009-12-17

申请号：US12543679

申请日：2009-08-19

申请人： EDUARD A. CARTIER ,  Steven J. Koester ,  Kingsuk Maitra ,  Arnlan Majumdar ,  Renee T. Mo

发明人： EDUARD A. CARTIER ,  Steven J. Koester ,  Kingsuk Maitra ,  Arnlan Majumdar ,  Renee T. Mo

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78696

摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.

公开(公告)号：US20090243031A1

公开(公告)日：2009-10-01

申请号：US12055682

申请日：2008-03-26

申请人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

发明人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

IPC分类号： H01L29/49 ,  H01L21/441

CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L29/517

摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

摘要翻译： 在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。

公开(公告)号：US07358130B2

公开(公告)日：2008-04-15

申请号：US11482419

申请日：2006-07-07

申请人： Bachir Dirahoui ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Eric P. Solecky

发明人： Bachir Dirahoui ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Eric P. Solecky

IPC分类号： H01L21/8238

CPC分类号： H01L22/12

摘要： A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measurement at at least one location along each thick, thin and transition spacer regions; determining a threshold LWR measurement value based on the LWR measurements; defining a region of interest (ROI) and obtaining a further LWR measurement in the ROI; comparing the LWR measurement in the ROI against the threshold LWR measurement value; and, notifying a user that either encroachment of the spacer structure is present when the LWR measurement in the ROI is below the threshold LWR measurement value, or that no encroachment of the spacer structure is present when the LWR measurement in the ROI is above the threshold LWR measurement value.

摘要翻译： 一种实现用于确定具有厚而薄的间隔区域的半导体器件中间隔结构的侵入的步骤的方法，包括在它们之间形成的过渡区域。 方法步骤包括：在沿着每个厚的，薄的和过渡间隔区的至少一个位置处获得线宽粗糙度（LWR）测量; 基于LWR测量确定阈值LWR测量值; 定义感兴趣区域（ROI）并在ROI中获得进一步的LWR测量; 将ROI中的LWR测量值与阈值LWR测量值进行比较; 并且当ROI中的LWR测量低于阈值LWR测量值时或者当ROI中的LWR测量高于阈值时不通知间隔物结构的侵入，通知用户是否存在间隔结构的侵入 LWR测量值。