公开(公告)号：US11217285B1

公开(公告)日：2022-01-04

申请号：US16986116

申请日：2020-08-05

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

IPC: G11C7/22 ,  G11C7/10 ,  G06F11/10

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

公开(公告)号：US20200301615A1

公开(公告)日：2020-09-24

申请号：US16896027

申请日：2020-06-08

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G06F3/06

Abstract: An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

公开(公告)号：US20200159463A1

公开(公告)日：2020-05-21

申请号：US16751975

申请日：2020-01-24

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

公开(公告)号：US20200065028A1

公开(公告)日：2020-02-27

申请号：US16112624

申请日：2018-08-24

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G06F3/06

Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

公开(公告)号：US09396778B1

公开(公告)日：2016-07-19

申请号：US14820815

申请日：2015-08-07

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani

IPC: G11C7/06 ,  G11C7/22 ,  G11C7/00 ,  G11C7/10

CPC classification number: G11C7/1009 ,  G06F13/1689 ,  G11C7/00 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A method and apparatus for conditional cancellation of a calibration procedure is performed. In one embodiment, a memory controller is coupled to memory. The memory controller is configured to convey data and a data strobe signal to the memory. The memory controller may conduct calibrations of a delay of the data strobe signal to ensure sufficient setup and hold time for the data. After an initial calibration, and at each of a number of periodic intervals, the memory controller may determine whether one or more parameters is within a specified range. If one of the one or more parameters is not within its respective specified range, another calibration of the data strobe delay may be performed. However, if each of the one or more parameters is within its respective specified range, the calibration may be canceled.

Abstract translation: 执行用于校准过程的条件消除的方法和装置。 在一个实施例中，存储器控制器耦合到存储器。 存储器控制器被配置为将数据和数据选通信号传送到存储器。 存储器控制器可以进行数据选通信号的延迟的校准，以确保数据的足够的建立和保持时间。 在初始校准之后，并且在多个周期性间隔的每一个周期，存储器控制器可以确定一个或多个参数是否在指定范围内。 如果一个或多个参数中的一个不在其相应的指定范围内，则可执行数据选通延迟的另一校准。 然而，如果一个或多个参数中的每一个在其各自的指定范围内，则可以取消校准。

公开(公告)号：US09384820B1

公开(公告)日：2016-07-05

申请号：US14738119

申请日：2015-06-12

Applicant: Apple Inc.

Inventor： Neeraj Parik ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1636 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4096 ,  G11C2211/4061

Abstract: A method and apparatus for aligning calibration segments for increased availability of a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto via a number of independently operable channels (interfaces). The memory controller may convey on each of the channels at least one corresponding data strobe signal. The data strobe signal in each channel may be periodically calibrated. The memory controller may be configured to align the periodic calibrations in time so that they are performed concurrently instead of in a staggered manner. During the time the calibrations are performed on each channel, the memory may be unavailable for normal accesses.

Abstract translation: 公开了一种用于对准校准段以提高存储器子系统的可用性的方法和装置。 在一个实施例中，存储器子系统包括存储器和经由多个可独立操作的通道（接口）耦合到其上的存储器控​​制器。 存储器控制器可以在每个通道上传送至少一个对应的数据选通信号。 可以周期地校准每个通道中的数据选通信号。 存储器控制器可以被配置为在时间上对准周期性校准，使得它们同时执行而不是以交错方式执行。 在每个通道执行校准时，存储器可能无法正常访问。

公开(公告)号：US20160034219A1

公开(公告)日：2016-02-04

申请号：US14450525

申请日：2014-08-04

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Neeraj Parik ,  Kai Lun Hsiung

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0683 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1689

Abstract: A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit.The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. The memory interface unit may be configured to operate in a normal mode and a low power mode. However, in response to an occurrence of a given predetermined interval while the memory interface unit is in the low power mode, the memory interface unit may be configured to calibrate the timing unit subsequent to transitioning to the normal mode.

Abstract translation: 系统包括具有一个或多个存储阵列的存储器单元，以及可以耦合在存储器控制器和存储器单元之间的存储器接口单元。 存储器接口单元可以包括可以生成用于控制对存储器单元的读取和写入访问的定时信号的定时单元，以及可以以预定间隔校准定时单元的控制单元。 存储器接口单元可以被配置为在正常模式和低功率模式下操作。 然而，响应于在存储器接口单元处于低功率模式时发生给定的预定间隔，存储器接口单元可以被配置为在转换到正常模式之后校准定时单元。