公开(公告)号：US06583871B1

公开(公告)日：2003-06-24

申请号：US09911238

申请日：2001-07-23

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Khoi A. Phan ,  Ramkumar Subramanian

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Khoi A. Phan ,  Ramkumar Subramanian

IPC分类号： G01N2100

CPC分类号： G01N21/956 ,  G01N21/9501

摘要： A system adapted to provide in-situ detection of closed area defects and a method for the same is provided. The system comprises a light source for directing light on to a wafer having a grating pattern etched thereon; a light detector for collecting the light reflected from the wafer; a processor operatively coupled to the light detector for converting the collected light into data associated with the grating pattern and determining the presence of the closed area defect; and a controller operatively coupled to the processor for determining whether the wafer requires additional processing to repair the closed area defect.

摘要翻译： 提供一种适于提供闭合区域缺陷的原位检测的系统及其方法。 该系统包括用于将光引导到具有蚀刻在其上的光栅图案的晶片的光源; 用于收集从晶片反射的光的光检测器; 处理器，其可操作地耦合到所述光检测器，用于将所收集的光转换成与所述光栅图案相关联的数据，并确定所述封闭区域缺陷的存在; 以及可操作地耦合到所述处理器的控制器，用于确定所述晶片是否需要额外的处理以修复所述封闭区域缺陷。

公开(公告)号：US06579651B2

公开(公告)日：2003-06-17

申请号：US10175923

申请日：2002-06-20

申请人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan

发明人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan

IPC分类号： G03F900

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70441

摘要： The present invention relates to a system and method of modifying mask layout data to improve the fidelity of mask manufacture. The system and method include determining the difference between the mask layout design and the mask features as written, and generating sizing corrections. The sizing corrections can be used to modify the mask layout data, and/or stored in a database.

公开(公告)号：US06459482B1

公开(公告)日：2002-10-01

申请号：US09729294

申请日：2000-12-04

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

IPC分类号： G01J110

CPC分类号： H01J37/28 ,  H01J2237/2826

摘要： The present invention provides SEM systems, SEM calibration standards, and SEM calibration methods that improved accuracy in critical dimension measurements. The calibration standards have features formed with an amorphous material such as amorphous silicon. Amorphous materials lack the crystal grain structure of materials such as polysilicon and are capable of providing sharper edged features and higher accuracy patterns than grained materials. The amorphous material can be bound to a silicon wafer substrate through an intermediate layer of material, such as silicon dioxide. Where the intermediate layer is insulating material, as is silicon dioxide, the intermediate layer may be patterned with gaps to provide for electrical communication between the amorphous silicon and the silicon wafer. Charges imparted to the amorphous silicon during electron beam scanning may thereby drain to the silicon wafer rather than accumulating to a level where they would distort the electron beam.

摘要翻译： 本发明提供SEM系统，SEM校准标准和SEM校准方法，提高了临界尺寸测量的精度。 校准标准品具有非晶体材料如非晶硅形成的特征。 无定形材料缺乏诸如多晶硅的材料的晶粒结构，并且能够提供比颗粒材料更尖锐的边缘特征和更高精度的图案。 非晶材料可以通过诸如二氧化硅的材料的中间层与硅晶片衬底结合。 在中间层是绝缘材料的情况下，如二氧化硅那样，中间层可以用间隙图案化以提供非晶硅和硅晶片之间的电连通。 因此，在电子束扫描期间赋予非晶硅的电荷可以从而被排出到硅晶片，而不是积聚到它们会使电子束变形的水平。

公开(公告)号：US06190062B1

公开(公告)日：2001-02-20

申请号：US09558492

申请日：2000-04-26

申请人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Bryan K. Choo ,  Sanjay K. Yedur

发明人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Bryan K. Choo ,  Sanjay K. Yedur

IPC分类号： G03D1300

CPC分类号： H01J37/28 ,  H01J2237/2817

摘要： One aspect of the present invention relates to a method of inspecting a patterned substrate using an SEM, involving the steps of evaluating the patterned substrate to determine if charges exist thereon; introducing the patterned substrate having charges thereon into a processing chamber of the SEM; inspecting the patterned resist using an electron beam generated by the SEM; and introducing a cleaner containing ozone into the processing chamber of the SEM. Another aspect of the present invention relates to a system for processing a patterned substrate, containing a charge sensor for determining if charges exist on the patterned substrate and measuring the charges; a means for contacting the patterned substrate with a cleaner containing ozone to reduce the charges thereon; a controller for setting at least one of time of contact between the patterned substrate and the cleaner, temperature of the cleaner, concentration of ozone in the cleaner, and pressure under which contact between the patterned substrate and the cleaner occurs; and a device for inspecting the patterned substrate with an electron beam.

摘要翻译： 本发明的一个方面涉及使用SEM检查图案化衬底的方法，包括以下步骤：评估图案化衬底以确定其中是否存在电荷; 将具有电荷的图案化衬底引入到SEM的处理室中; 使用由SEM产生的电子束检查图案化的抗蚀剂; 并将含有臭氧的清洁剂引入SEM的处理室。 本发明的另一方面涉及一种用于处理图案化衬底的系统，其包含用于确定在图案化衬底上是否存在电荷并测量电荷的电荷传感器; 用于使图案化基底与含有臭氧的清洁剂接触以降低其上的电荷的装置; 用于设置图案化基板和清洁器之间的接触时间中的至少一个的控制器，清洁器的温度，清洁器中的臭氧浓度以及图案化基板和清洁器之间的接触发生的压力; 以及用于用电子束检查图案化衬底的装置。

公开(公告)号：US08028531B2

公开(公告)日：2011-10-04

申请号：US12537135

申请日：2009-08-06

申请人： Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh

发明人： Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh

IPC分类号： F25B21/02

CPC分类号： H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.

摘要翻译： 本发明提供一种通过采用具有热结构网工作组件的热调节装置来调节和监测集成电路的散热的系统和方法。 每个热结构可以用作导热通道，用于将热量从集成电路引入和/或散热，从而在半导体主体上产生更均匀的温度梯度。

公开(公告)号：US20090288425A1

公开(公告)日：2009-11-26

申请号：US12537135

申请日：2009-08-06

申请人： Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh

发明人： Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh

IPC分类号： F25B21/02 ,  G05D23/00

CPC分类号： H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.

摘要翻译： 本发明提供一种通过采用具有热结构网工作组件的热调节装置来调节和监测集成电路的散热的系统和方法。 每个热结构可以用作导热通道，用于将热量从集成电路引入和/或散热，从而在半导体主体上产生更均匀的温度梯度。

公开(公告)号：US07604903B1

公开(公告)日：2009-10-20

申请号：US10768515

申请日：2004-01-30

申请人： Bhanwar Singh ,  Srikanteswara Dakshina-Murthy ,  Khoi A. Phan ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Bhanwar Singh ,  Srikanteswara Dakshina-Murthy ,  Khoi A. Phan ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： G03F1/00 ,  G03F1/14

CPC分类号： G03F1/50

摘要： A mask is provided to be used with nanoprint lithography processes to facilitate reproduction of small features required for the production of integrated circuits. A translucent substrate is provided along with one or more three-dimensional features that include one or more vertical sidewalls. An absorbing material is deposited upon one or more of the vertical sidewalls so that light in an incident direction to an upper surface of the substrate will be absorbed by the absorbing material, resulting in light blocking features. One or more horizontal surfaces are formed upon one or more of the three-dimensional features, which allow light rays to exit a lower surface of the substrate unobstructed by the absorbing material.

摘要翻译： 提供掩模以与纳米印刷光刻工艺一起使用，以便于再现生产集成电路所需的小特征。 提供了一个半透明衬底以及包括一个或多个垂直侧壁的一个或多个三维特征。 吸收材料沉积在一个或多个垂直侧壁上，使得在衬底的上表面的入射方向上的光将被吸收材料吸收，导致阻光特征。 一个或多个水平表面形成在三维特征中的一个或多个上，这允许光线离开衬底的下表面而不被吸收材料阻挡。

公开(公告)号：US07449348B1

公开(公告)日：2008-11-11

申请号：US10858605

申请日：2004-06-02

申请人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan

发明人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan

IPC分类号： H01L21/00

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L22/12

摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.

摘要翻译： 本发明一般涉及光刻系统和方法，更具体地涉及有助于补偿压印掩模上逆行特征轮廓的系统和方法。 本发明的一个方面产生反馈信息，其通过使用散射测量系统来检测逆行特征轮廓，以及通过间隔回蚀程序来缓解逆行轮廓，从而有助于控制压印掩模特征轮廓。

公开(公告)号：US07221060B1

公开(公告)日：2007-05-22

申请号：US11074602

申请日：2005-03-08

申请人： Bhanwar Singh ,  Khoi A. Phan ,  Bharath Rangarajan ,  Iraj Emami ,  Ramkumar Subramanian

发明人： Bhanwar Singh ,  Khoi A. Phan ,  Bharath Rangarajan ,  Iraj Emami ,  Ramkumar Subramanian

IPC分类号： H01L23/544

CPC分类号： G03F7/70625 ,  G03F7/70633 ,  G03F9/7076 ,  Y10S438/975

摘要： Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.

摘要翻译： 公开了用于对准多层半导体器件制造工艺和/或利用复合对准标记的系统的多层的系统和/或方法。 提供组件以形成复合对准标记，使得复合对准标记的第一部分与晶片的层相关联，并且复合对准标记的第二部分与晶片的不同层相关联。 使用对准部件将待图案化的层的掩模版对准到复合对准标记。

公开(公告)号：US07109046B1

公开(公告)日：2006-09-19

申请号：US10768514

申请日：2004-01-30

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Khoi A. Phan

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Khoi A. Phan

IPC分类号： H01L21/00

CPC分类号： H01L22/12

摘要： The present invention relates generally to semiconductor processing, and more particularly to methods and systems for reducing costs of wafer production by analyzing key aspects of wafer status to determine whether to initiate corrective measures to salvage a wafer at an early stage and before substantial costs are incurred in fabricating a defective wafer. One aspect of the present invention provides for growing an oxide layer on a wafer upon a determination that an oxide layer on the wafer surface is absent or is present but inadequate. Another aspect of the present invention provides for a determination of whether to apply preemptory corrective treatment(s) to a wafer surface based on the presence and/or magnitude of nitrogen signatures in an extant oxide surface layer, which can indicate that an undesirable defect known as “footing” will occur during a post-exposure delay period. Thus, the invention advantageously reduces production costs by facilitating a most correct decision to mitigate the source(s) of potential defects at an early stage and, thus, before substantial costs are incurred in production of the wafer.

摘要翻译： 本发明一般涉及半导体处理，更具体地说，涉及通过分析晶片状态的关键方面来降低晶片生产成本的方法和系统，以确定是否启动在早期阶段挽救晶片的纠正措施以及在大量成本产生之前 在制造缺陷晶片时。 本发明的一个方面提供了在确定晶片表面上的氧化物层不存在或存在但不足的情况下，在晶片上生长氧化物层。 本发明的另一方面提供了根据现有氧化物表面层中氮标记的存在和/或大小来确定是否对晶片表面施加抢占式校正处理，其可以指示不期望的缺陷已知 因为在曝光后延迟期间将发生“立足”。 因此，本发明有利地通过促进最正确的决定来降低生产成本，以在早期阶段减轻潜在缺陷的来源，并且因此在生产晶片之前花费大量成本之前。