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    PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING READ OPERATION THEREOF
    31.
    发明申请
    PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING READ OPERATION THEREOF 审中-公开
    相变随机访问存储器及其读取操作的方法

    公开(公告)号：US20100220522A1

    公开(公告)日：2010-09-02

    申请号：US12777298

    申请日：2010-05-11

    申请人： Hyung-rok Oh ,  Mu-hui Park ,  Du-eung Kim

    发明人： Hyung-rok Oh ,  Mu-hui Park ,  Du-eung Kim

    IPC分类号： G11C11/00 ,  G11C8/08

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004

    摘要： A phase change random access memory is provided which includes a memory array including a plurality of phase change memory cells, and wordlines respectively connected to the phase change memory cells, where, in a read operation, a voltage of a wordline connected to a selected phase change memory cell is transitioned between at least two voltage stages having different voltage levels.

    摘要翻译： 提供了一种相变随机存取存储器，其包括包括多个相变存储器单元的存储器阵列和分别连接到相变存储单元的字线，其中在读操作中连接到所选相位的字线的电压 改变存储单元在具有不同电压电平的至少两个电压级之间转变。

    Phase change random access memory and method of controlling read operation thereof
    32.
    发明申请
    Phase change random access memory and method of controlling read operation thereof 审中-公开
    相变随机存取存储器及其读操作的控制方法

    公开(公告)号：US20070091665A1

    公开(公告)日：2007-04-26

    申请号：US11580087

    申请日：2006-10-13

    申请人： Hyung-rok Oh ,  Mu-hui Park ,  Du-eung Kim

    发明人： Hyung-rok Oh ,  Mu-hui Park ,  Du-eung Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004

    摘要： A phase change random access memory is provided which includes a memory array including a plurality of phase change memory cells, and wordlines respectively connected to the phase change memory cells, where, in a read operation, a voltage of a wordline connected to a selected phase change memory cell is transitioned between at least two voltage stages having different voltage levels.

    摘要翻译： 提供了一种相变随机存取存储器，其包括包括多个相变存储器单元的存储器阵列和分别连接到相变存储单元的字线，其中在读操作中连接到所选相位的字线的电压 改变存储单元在具有不同电压电平的至少两个电压级之间转变。

    Phase-change semiconductor memory device and method of programming the same
    33.
    发明授权
    Phase-change semiconductor memory device and method of programming the same 有权
    相变半导体存储器件及其编程方法

    公开(公告)号：US07436693B2

    公开(公告)日：2008-10-14

    申请号：US11319372

    申请日：2005-12-29

    申请人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh

    发明人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0038 ,  G11C2013/0078

    摘要： In one aspect, a semiconductor memory device includes a plurality of phase-change memory cells which are programmed according to a write current applied to the phase-change memory cells, a voltage boosting circuit which receives a first voltage and outputs a boosted voltage which is greater than the first voltage, and a write driver which receives the boosted voltage and which generates the write current from the boosted voltage. In another aspect, the write driver generates the write current corresponding to one of a set current pulse and a reset current pulse, and at least one of the set current pulse and the reset current pulse is gradually increased.

    摘要翻译： 一方面，半导体存储器件包括根据施加到相变存储单元的写入电流进行编程的多个相变存储器单元，接收第一电压并输出升压电压的升压电路， 大于第一电压的写驱动器，以及接收升压电压并从升压电压产生写电流的写驱动器。 在另一方面，写入驱动器产生与设定电流脉冲和复位电流脉冲中的一个对应的写入电流，并且设定电流脉冲和复位电流脉冲中的至少一个逐渐增加。

    Phase-change semiconductor memory device and method of programming the same
    34.
    发明申请
    Phase-change semiconductor memory device and method of programming the same 有权
    相变半导体存储器件及其编程方法

    公开(公告)号：US20060220071A1

    公开(公告)日：2006-10-05

    申请号：US11319372

    申请日：2005-12-29

    申请人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh

    发明人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh

    IPC分类号： H01L29/768

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0038 ,  G11C2013/0078

    摘要： In one aspect, a semiconductor memory device includes a plurality of phase-change memory cells which are programmed according to a write current applied to the phase-change memory cells, a voltage boosting circuit which receives a first voltage and outputs a boosted voltage which is greater than the first voltage, and a write driver which receives the boosted voltage and which generates the write current from the boosted voltage. In another aspect, the write driver generates the write current corresponding to one of a set current pulse and a reset current pulse, and at least one of the set current pulse and the reset current pulse is gradually increased.

    摘要翻译： 一方面，半导体存储器件包括根据施加到相变存储单元的写入电流进行编程的多个相变存储器单元，接收第一电压并输出升压电压的升压电路， 大于第一电压的写驱动器，以及接收升压电压并从升压电压产生写电流的写驱动器。 在另一方面，写入驱动器产生与设定电流脉冲和复位电流脉冲中的一个对应的写入电流，并且设定电流脉冲和复位电流脉冲中的至少一个逐渐增加。

    Phase change random access memory, boosting charge pump and method of generating write driving voltage
    35.
    发明授权
    Phase change random access memory, boosting charge pump and method of generating write driving voltage 有权
    相变随机存取存储器，升压电荷泵和产生写驱动电压的方法

    公开(公告)号：US07352616B2

    公开(公告)日：2008-04-01

    申请号：US11319602

    申请日：2005-12-29

    申请人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

    发明人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

    IPC分类号： G11C11/00

    CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009

    摘要： A phase change random access memory on aspect includes a memory cell array block including a plurality of phase change memory cells, a column decoder, a row decoder, a column selector, and a write driver. The memory further includes a write boosting unit having a plurality of internal charge pumps which boost a first voltage to generate a write driving voltage which drives the write driver, where the number of internal charge pumps that are activated during a write operation is varied according to a number of phase change memory cells which are selected during the write operation. The memory still further includes a column boosting unit which boosts the first voltage to generate a column driving voltage which drives the column decoder, and a row boosting unit which boosts the first voltage to generate a row driving voltage which drives the row decoder.

    摘要翻译： 一方面的相变随机存取存储器包括包括多个相变存储器单元，列解码器，行解码器，列选择器和写驱动器的存储单元阵列块。 存储器还包括具有多个内部电荷泵的写入升压单元，该多个内部电荷泵升压第一电压以产生驱动写入驱动器的写入驱动电压，其中在写入操作期间被激活的内部电荷泵的数量根据 在写入操作期间选择的多个相变存储器单元。 存储器还包括列升压单元，其升高第一电压以产生驱动列解码器的列驱动电压;以及行升压单元，其升高第一电压以产生驱动行解码器的行驱动电压。

    Phase change random access memory, boosting charge pump and method of generating write driving voltage
    36.
    发明申请
    Phase change random access memory, boosting charge pump and method of generating write driving voltage 有权
    相变随机存取存储器，升压电荷泵和产生写驱动电压的方法

    公开(公告)号：US20070097741A1

    公开(公告)日：2007-05-03

    申请号：US11319602

    申请日：2005-12-29

    申请人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

    发明人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

    IPC分类号： G11C11/00

    CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009

    摘要： A phase change random access memory on aspect includes a memory cell array block including a plurality of phase change memory cells, a column decoder, a row decoder, a column selector, and a write driver. The memory further includes a write boosting unit having a plurality of internal charge pumps which boost a first voltage to generate a write driving voltage which drives the write driver, where the number of internal charge pumps that are activated during a write operation is varied according to a number of phase change memory cells which are selected during the write operation. The memory still further includes a column boosting unit which boosts the first voltage to generate a column driving voltage which drives the column decoder, and a row boosting unit which boosts the first voltage to generate a row driving voltage which drives the row decoder.

    摘要翻译： 一方面的相变随机存取存储器包括包括多个相变存储器单元，列解码器，行解码器，列选择器和写驱动器的存储单元阵列块。 存储器还包括具有多个内部电荷泵的写入升压单元，该多个内部电荷泵升压第一电压以产生驱动写入驱动器的写入驱动电压，其中在写入操作期间被激活的内部电荷泵的数量根据 在写入操作期间选择的多个相变存储器单元。 存储器还包括列升压单元，其升高第一电压以产生驱动列解码器的列驱动电压;以及行升压单元，其升高第一电压以产生驱动行解码器的行驱动电压。

    Phase change memory device
    37.
    发明申请
    Phase change memory device 有权
    相变存储器件

    公开(公告)号：US20070159878A1

    公开(公告)日：2007-07-12

    申请号：US11648558

    申请日：2007-01-03

    申请人： Byung-gil Choi ,  Du-eung Kim ,  Woo-yeong Cho

    发明人： Byung-gil Choi ,  Du-eung Kim ,  Woo-yeong Cho

    IPC分类号： G11C5/06 ,  G11C11/00 ,  G11C8/00

    CPC分类号： G11C7/18 ,  G11C8/12 ,  G11C13/0004 ,  G11C2213/72 ,  G11C2213/79

    摘要： A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines. The plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.

    摘要翻译： 相变存储器件包括：半导体衬底，其包括多个相变存储器单元;多个局部位线，其延伸在所述半导体衬底上;所述多个局部位线中的每一个耦合到所述多个相变存储器单元; 以及在所述多个局部位线上延伸的多个全局位线，所述多个全局位线中的每一条选择性地耦合到所述多个局部位线。 多个全局位线位于半导体衬底上的两个或更多个不同的布线层上。

    Resistive memory device and method of writing data
    38.
    发明授权
    Resistive memory device and method of writing data 有权
    电阻式存储器件及数据写入方法

    公开(公告)号：US07859882B2

    公开(公告)日：2010-12-28

    申请号：US11844511

    申请日：2007-08-24

    申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

    发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

    IPC分类号： G11C11/00

    CPC分类号： G11C8/14 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2213/79

    摘要： A resistive memory device is provided. The resistive memory device includes word lines arranged in M rows, bit lines arranged in N columns, local source lines arranged in M/2 rows, and resistive memory cells arranged in M rows and N columns. Each of the resistive memory cells includes a resistance variable element having a first electrode connected to a corresponding bit line, and a cell transistor having a first terminal connected to a second electrode of the resistance variable element, a second terminal connected to a corresponding local source line, and a control terminal connected to a corresponding word line. The local source line is commonly connected to the second terminals of the cell transistors of the two neighboring rows.

    摘要翻译： 提供了一种电阻式存储器件。 电阻式存储装置包括排列成M行的字线，以N列排列的位线，以M / 2行排列的局部源极线以及布置成M行N列的电阻存储单元。 每个电阻存储单元包括电阻可变元件，电阻可变元件具有连接到对应的位线的第一电极，以及单元晶体管，其具有连接到电阻可变元件的第二电极的第一端子，连接到相应的本地源极的第二端子 线路和连接到相应字线的控制终端。 本地源极线通常连接到两个相邻行的单元晶体管的第二端子。