ELECTROMECHANICAL MEMORY ARRAY USING NANOTUBE RIBBONS AND METHOD FOR MAKING SAME
    32.
    发明申请
    ELECTROMECHANICAL MEMORY ARRAY USING NANOTUBE RIBBONS AND METHOD FOR MAKING SAME 有权
    使用纳米碳管的机电存储器阵列及其制造方法

    公开(公告)号:US20090283803A1

    公开(公告)日:2009-11-19

    申请号:US12415247

    申请日:2009-03-31

    IPC分类号: H01L27/08 H01L21/82

    摘要: Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or more nanotubes. The electro-mechanical circuit elements are made by providing a structure having electrically conductive traces and supports, in which the supports extend from a surface of the substrate. A layer of nanotubes is provided over the supports, and portions of the layer of nanotubes are selectively removed to form ribbons of nanotubes that cross the electrically conductive traces. Each ribbon includes one or more nanotubes.

    摘要翻译: 公开了诸如存储单元的机电电路及其制造方法。 这些电路包括具有导电迹线和从衬底表面延伸的支撑体的结构,以及由支撑体悬挂的穿过导电迹线的纳米管带,其中每个带包括一个或多个纳米管。 电 - 机械电路元件通过提供具有导电迹线和支撑件的结构来制造,其中支撑件从基板的表面延伸。 在载体上提供一层纳米管,并且选择性地去除纳米管层的部分以形成穿过导电迹线的纳米管带。 每个带包括一个或多个纳米管。

    Nanotube-on-gate FET structures and applications
    33.
    发明授权
    Nanotube-on-gate FET structures and applications 有权
    纳米管栅极FET结构和应用

    公开(公告)号:US07294877B2

    公开(公告)日:2007-11-13

    申请号:US10811373

    申请日:2004-03-26

    IPC分类号: H01L51/30

    摘要: Nanotube on gate FET structures and applications of such, including n2 crossbars requiring only 2n control lines. A non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and a channel region of a second semiconductor type of material disposed between the source and drain region. A gate structure is made of at least one of semiconductive or conductive material and is disposed over an insulator over the channel region. A control gate is made of at least one of semiconductive or conductive material. An electromechanically-deflectable nanotube switching element is in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure. The network is such that the nanotube switching element is deflectable into contact with the other of the gate structure and the control gate structure in response to signals being applied to the control gate and one of the source region and drain region. Certain embodiments of the device have an area of about 4 F2. Other embodiments include a release line is positioned in spaced relation to the nanotube switching element, and having a horizontal orientation that is parallel to the orientation of the source and drain diffusions. Other embodiments provide an n2 crossbar array having n2 non-volatile transistor devices, but require only 2n control lines.

    摘要翻译: 纳米管栅极FET结构及其应用,包括只需要2n条控制线的n 2条交叉。 非挥发性晶体管器件包括第一半导体类型的材料的源极区域和漏极区域以及设置在源极和漏极区域之间的第二半导体类型的材料的沟道区域。 栅极结构由半导体或导电材料中的至少一种制成,并且设置在沟道区域上方的绝缘体上。 控制门由半导体或导电材料中的至少一种制成。 机电偏转型纳米管开关元件与栅极结构和控制栅极结构中的一个固定接触,并且不与栅极结构和控制栅极结构中的另一个固定接触。 该器件具有固有电容的网络,包括相对于栅极结构的未折射的纳米管开关元件的固有电容。 网络使得纳米管开关元件响应于施加到控制栅极和源极区域和漏极区域之一的信号而偏转成与栅极结构和控制栅极结构中的另一个接触。 该装置的某些实施例具有约4F 2的面积。 其他实施例包括释放线与纳米管开关元件间隔开定位,并且具有平行于源极和漏极扩散的取向的水平取向。 其他实施例提供了具有n 2个非易失性晶体管器件的n≥2的交叉开关阵列,但是仅需要2n个控制线。

    Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same
    36.
    发明授权
    Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same 有权
    非挥发性纳米管二极管和非易失性纳米管块及使用其的系统及其制造方法

    公开(公告)号:US07782650B2

    公开(公告)日:2010-08-24

    申请号:US11835845

    申请日:2007-08-08

    IPC分类号: G11C11/00

    摘要: Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode element, and a nanotube fabric article capable of multiple resistance states. The semiconductor diode and nanotube article are between and in electrical communication with the first and second terminals, which are coupled to the word line bit line respectively. The operation circuit selects cells by activating bit and/or word lines, detects a resistance state of the nanotube fabric article of a selected memory cell, and adjusts electrical stimulus applied to the cell to controllably induce a selected resistance state in the nanotube fabric article. The selected resistance state corresponds to an informational state of the memory cell.

    摘要翻译: 在一个方面,存储器阵列包括字线; 位线 记忆细胞; 和存储器操作电路。 每个存储器单元响应于字线和位线上的电刺激,并且包括:具有第一和第二端子的二端非易失性纳米管开关器件,半导体二极管元件和能够具有多个电阻状态的纳米管织物制品 。 半导体二极管和纳米管制品分别与第一和第二端子电连接,并且与第一和第二端子电连接,它们分别耦合到字线位线。 操作电路通过激活位和/或字线来选择单元,检测所选择的存储单元的纳米管织物的电阻状态,并调整施加到单元的电刺激以可控制地引起纳米管织物制品中选定的电阻状态。 选择的电阻状态对应于存储单元的信息状态。