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    Programmable logic device macrocell with improved logic capability
    32.
    发明授权
    Programmable logic device macrocell with improved logic capability 失效
    具有改进逻辑能力的可编程逻辑器件宏单元

    公开(公告)号：US06366119B1

    公开(公告)日：2002-04-02

    申请号：US09677156

    申请日：2000-10-02

    申请人： Bruce B. Pedersen ,  John C. Costello

    发明人： Bruce B. Pedersen ,  John C. Costello

    IPC分类号： H03K19177

    CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17748

    摘要： A macrocell for a programmable logic device includes circuitry for allowing a neighboring macrocell to borrow various numbers of the product terms of the macrocell. The macrocell can continue to make full use of its product terms that are not thus borrowed. This includes logically combining and registering the unborrowed product terms. The macrocell may include circuitry for feeding back to the AND array of the programmable logic device a combinatorial or registered signal of the macrocell, and also outputting such a combinatorial or registered signal from the macrocell. When a combinatorial signal is fed back, the register of the macrocell can be used for another signal of the macrocell.

    摘要翻译： 用于可编程逻辑器件的宏单元包括用于允许相邻宏单元借用宏单元的各种数量的乘积项的电路。 宏单元可以继续充分利用其不被借用的产品术语。 这包括逻辑上组合和注册未管理的产品术语。 宏单元可以包括用于将可编程逻辑器件的AND阵列反馈给宏单元的组合或注册信号的电路，并且还从宏单元输出这样的组合或注册信号。 当反馈组合信号时，宏单元的寄存器可用于宏单元的另一个信号。

    Programmable logic device with carry look-ahead
    33.
    发明授权
    Programmable logic device with carry look-ahead 有权
    可编程逻辑器件带有前瞻性

    公开(公告)号：US06359468B1

    公开(公告)日：2002-03-19

    申请号：US09516865

    申请日：2000-03-02

    申请人： James Park ,  Wei-Jen Huang ,  Tony Ngai ,  Bruce B. Pedersen

    发明人： James Park ,  Wei-Jen Huang ,  Tony Ngai ,  Bruce B. Pedersen

    IPC分类号： H03K19177

    CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17792

    摘要： A programmable logic device is adapted to predict carry values in long-chain-carry logic configurations. In the most preferred embodiment, which functions in any long-carry-chain logic configuration, each logic region calculates a result for both values of the carry-in signal to that region, and when a carry signal for the group to which the region belongs reaches the region, the correct result in each region, and thence the correct carry-out for that group, are calculated and propagated. The carry-out terminal of one group is arranged to be adjacent to the carry-in terminal of the next group, to enhance carry propagation speed. In another embodiment, each region looks back two regions to predict the carry-in. In two additional embodiments, logic is provided to mathematically calculate the carry values.

    摘要翻译： 可编程逻辑器件适用于预测长链进位逻辑配置中的进位值。 在最优选的实施例中，其在任何长承载链逻辑配置中起作用，每个逻辑区域计算对于该区域的进位信号的两个值的结果，以及当该区域所属的组的进位信号 到达该地区，每个地区的正确结果，然后计算和传播该组的正确进行。 一组的进位终端被布置成与下一组的进位终端相邻，以提高进位传播速度。 在另一个实施例中，每个区域回顾两个区域以预测携带。 在两个附加实施例中，提供逻辑以在数学上计算进位值。

    Programmable logic device with redundant circuitry
    34.
    发明授权
    Programmable logic device with redundant circuitry 有权
    具有冗余电路的可编程逻辑器件

    公开(公告)号：US06344755B1

    公开(公告)日：2002-02-05

    申请号：US09691424

    申请日：2000-10-18

    申请人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

    发明人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

    IPC分类号： H03K19003

    CPC分类号： H03K19/17764 ,  H03K19/17736

    摘要： A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows. The partially overlapping pattern allows the connections to be less regular, which increases flexibility when routing signals on the device.

    摘要翻译： 提供了一种可编程逻辑器件，其允许在器件上的可编程逻辑行中检测到缺陷时将冗余的可编程逻辑行移位到位以修复器件。 通过将编程数据路由到正常逻辑和冗余逻辑中来绕过包含缺陷的逻辑行，将冗余行移位到位。 开关电路可用于将编程数据引导到各种数据寄存器的串行输入，然后将其用于将编程数据加载到器件中。 在设备上的可编程逻辑区域和垂直和水平导体之间进行的可编程连接的模式也允许将冗余逻辑移位到位。 逻辑和水平和垂直导体之间的一些连接可以在列内相同以便于移动。 其他连接可能仅在相应行之间部分重叠。 部分重叠的模式允许连接不太规则，这在设备上路由信号时增加灵活性。

    Programmable logic devices with enhanced multiplexing capabilities
    36.
    发明授权
    Programmable logic devices with enhanced multiplexing capabilities 有权
    具有增强复用功能的可编程逻辑器件

    公开(公告)号：US06255846B1

    公开(公告)日：2001-07-03

    申请号：US09519314

    申请日：2000-03-06

    申请人： Andy L. Lee ,  Christopher F. Lane ,  Bruce B. Pedersen

    发明人： Andy L. Lee ,  Christopher F. Lane ,  Bruce B. Pedersen

    IPC分类号： G06F738

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17728

    摘要： Programmable logic modules on a programmable logic device each include a four-input look-up table circuit which can be programmed to allow the logic module to produce an output signal which can be any of a plurality of logical combinations of four input signals applied to the logic module. In addition, each logic module is augmented with additional circuitry that allows the logic module to be alternatively operated as a dynamic four-to-one multiplexer.

    摘要翻译： 可编程逻辑器件上的可编程逻辑模块均包括四输入查找表电路，其可被编程以允许逻辑模块产生输出信号，输出信号可以是四个输入信号的多个逻辑组合中的任何一个， 逻辑模块。 此外，每个逻辑模块都增加了额外的电路，允许逻辑模块交替地作为动态四对一多路复用器操作。

    Programmable logic device having quadrant layout
    37.
    发明授权
    Programmable logic device having quadrant layout 有权
    具有象限布局的可编程逻辑器件

    公开(公告)号：US06218859B1

    公开(公告)日：2001-04-17

    申请号：US09320007

    申请日：1999-05-26

    申请人： Bruce B. Pedersen

    发明人： Bruce B. Pedersen

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/17796

    摘要： Disclosed is a programmable logic device (PLD) that includes logic cells that can be allocated among zones and are preferably allocated among four quadrants. I/O pins are permanently associated with a quadrant by placing the I/O pins along an exterior edge of that quadrant. Logic cells which are located in a quadrant are directly connected to I/O pins which are permanently associated with that quadrant. Even if additional logic cells are added to the PLD without changing the number of I/O pins, the I/O pins located along an exterior edge of a quadrant will still be directly connected to the logic cells in that quadrant. Thus, a user can determine whether use of a given I/O pin and logic cell, regardless of the number of logic cells in the PLD, will result in an inter-quadrant signal transmission delay.

    摘要翻译： 公开了一种可编程逻辑器件（PLD），其包括可以在区域之间分配的逻辑单元，并且优选地在四个象限之间分配。 I / O引脚通过沿着该象限的外部边缘放置I / O引脚而永久地与象限相关联。 位于象限中的逻辑单元直接连接到与该象限永久关联的I / O引脚。 即使在不改变I / O引脚数量的情况下将额外的逻辑单元添加到PLD中，沿着象限的外部边缘定位的I / O引脚仍将直接连接到该象限中的逻辑单元。 因此，用户可以确定使用给定的I / O引脚和逻辑单元，无论PLD中的逻辑单元的数量如何，将导致象限间信号传输延迟。

    Programmable logic array integrated circuit devices
    39.
    发明授权
    Programmable logic array integrated circuit devices 失效
    可编程逻辑阵列集成电路器件

    公开(公告)号：US5986470A

    公开(公告)日：1999-11-16

    申请号：US970830

    申请日：1997-11-14

    申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

    发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

    摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

    摘要翻译： 可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。