公开(公告)号：US20080001209A1

公开(公告)日：2008-01-03

申请号：US11783548

申请日：2007-04-10

申请人： Eun-Suk Cho ,  Kyu-Charn Park ,  Jong-Jin Lee ,  Jeong-Dong Choe

发明人： Eun-Suk Cho ,  Kyu-Charn Park ,  Jong-Jin Lee ,  Jeong-Dong Choe

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336

摘要： A non-volatile memory device may include a substrate having a field region and an active region including a rounded upper edge portion and a flat upper central portion, an effective tunnel oxide layer on the flat upper central portion of the active region, a split floating gate electrode on the effective tunnel oxide layer, the floating gate electrode having a width greater than a width of the effective tunnel oxide layer, a dielectric layer pattern on the floating gate electrode, the dielectric layer pattern including metal oxide, and a control gate electrode on the dielectric layer pattern.

摘要翻译： 非易失性存储器件可以包括具有场区域和包括圆形上边缘部分和平坦上中心部分的有源区域的基板，在有源区域的平坦上中心部分上的有效隧道氧化物层，分裂浮动 栅极电极在有效隧道氧化物层上，浮栅电极的宽度大于有效隧道氧化物层的宽度，浮栅电极上的电介质层图案，包括金属氧化物的电介质层图案和控制栅电极 在电介质层图案上。

公开(公告)号：US07230294B2

公开(公告)日：2007-06-12

申请号：US10975933

申请日：2004-10-28

申请人： Chang-Hyun Lee ,  Kyu-Charn Park

发明人： Chang-Hyun Lee ,  Kyu-Charn Park

IPC分类号： G11C7/00 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

公开(公告)号：US07061044B2

公开(公告)日：2006-06-13

申请号：US10797754

申请日：2004-03-09

申请人： Kyu-Charn Park ,  Kwang-Shik Shin ,  Sung-Nam Chang

发明人： Kyu-Charn Park ,  Kwang-Shik Shin ,  Sung-Nam Chang

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/42328

摘要： A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.

摘要翻译： 非易失性存储器件包括栅极线，栅极线包括依次堆叠的栅极介电层，底部栅极图案，栅极间电介质和顶栅极图案。 栅极间电介质的宽度比底栅图案的宽度窄。

公开(公告)号：US06936885B2

公开(公告)日：2005-08-30

申请号：US10921656

申请日：2004-08-19

申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

IPC分类号： H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76802 ,  H01L27/115 ,  H01L27/11524

摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

公开(公告)号：US06586804B2

公开(公告)日：2003-07-01

申请号：US09949110

申请日：2001-09-07

申请人： Jung-Dal Choi ,  Kyu-Charn Park ,  Dong-Seog Eun

发明人： Jung-Dal Choi ,  Kyu-Charn Park ,  Dong-Seog Eun

IPC分类号： H01L2978

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11541 ,  Y10S438/981

摘要： A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.

公开(公告)号：US06380032B1

公开(公告)日：2002-04-30

申请号：US09724152

申请日：2000-11-28

申请人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

发明人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： Provided are a non-volatile flash memory device and a method of making the non-volatile flash memory device. A common source line is formed simultaneously with the formation of stacked transistors. The common source line is formed of the same material layer as floating gate pattern. The common source region and a scribe line region are simultaneously formed thorough the same photolithography process in a semiconductor substrate. Additionally, the common source line and butted contact are patterned simultaneously through the same photolithography process. Accordingly, the common source line process can be advantageously completed with very low cost and simplicity.

摘要翻译： 提供了一种非易失性闪存设备和制造非易失性闪存设备的方法。 共同的源极线与堆叠晶体管的形成同时形成。 公共源极线由与浮动栅极图案相同的材料层形成。 在半导体衬底中通过相同的光刻工艺同时形成公共源极区域和划线区域。 此外，通过相同的光刻工艺，共同的源极线和对接的触点被图案化。 因此，可以以非常低的成本和简单性有利地完成公共源线处理。

公开(公告)号：US06181014B2

公开(公告)日：2001-01-30

申请号：US09271519

申请日：1999-03-18

申请人： Kyu-Charn Park ,  Duck-Hyung Lee

发明人： Kyu-Charn Park ,  Duck-Hyung Lee

IPC分类号： H01L2348

CPC分类号： H01L27/10858 ,  H01L27/10885 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

摘要： Integrated circuit memory devices having highly integrated SOI memory cells therein include an SOI substrate having a semiconductor active layer therein. A first trench isolation region is also provided. The first trench isolation region extends into and partitions the semiconductor active layer into first and second active regions. These first and second active regions are preferably electrically isolated from each other by the first trench isolation region. First and second access transistors are provided in the first and second active regions, respectively, and a first electrically insulating layer is provided on the SOI substrate. A first bit line is also provided at a first level. The first bit line is electrically connected to a first source/drain region of the first access transistor by a first bit line contact. This first bit line contact extends through the first electrically insulating layer and contacts the first source/drain region of the first access transistor. A second electrically insulating layer is also provided on the first bit line, opposite said first electrically insulating layer and a second bit line is provided on the second electrically insulating layer at a second level above the first level. The second bit line is electrically connected to a first source/drain region of the second access transistor by a second bit line contact which extends through the first and second electrically insulating layers and contacts the first source/drain region of the second access transistor. Higher integration densities can be achieved by dividing the active layer into electrically isolated active regions and then forming bit lines at different levels which are electrically connected to access transistors within these isolated active regions.

摘要翻译： 其中具有高度集成的SOI存储单元的集成电路存储器件包括其中具有半导体有源层的SOI衬底。 还提供了第一沟槽隔离区域。 第一沟槽隔离区延伸到半导体活性层并将其分隔成第一和第二有源区。 这些第一和第二有源区优选地通过第一沟槽隔离区彼此电隔离。 第一和第二存取晶体管分别设置在第一和第二有源区中，并且第一电绝缘层设置在SOI衬底上。 在第一级还提供第一位线。 第一位线通过第一位线接触电连接到第一存取晶体管的第一源极/漏极区域。 该第一位线接触件延伸穿过第一电绝缘层并接触第一存取晶体管的第一源极/漏极区域。 在第一位线上还设有第二电绝缘层，与第一电绝缘层相对，并且第二位线在第二电绝缘层上设置在高于第一电平的第二电平上。 第二位线通过延伸穿过第一和第二电绝缘层并接触第二存取晶体管的第一源/漏区的第二位线接触电连接到第二存取晶体管的第一源/漏区。 可以通过将有源层分为电隔离的有源区，然后形成与这些隔离的有源区内的存取晶体管电连接的不同电平的位线来实现更高的积分密度。

公开(公告)号：US08076713B2

公开(公告)日：2011-12-13

申请号：US12422862

申请日：2009-04-13

申请人： Chang-Hyun Lee ,  Kyu-Charn Park

发明人： Chang-Hyun Lee ,  Kyu-Charn Park

IPC分类号： H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

摘要翻译： 非易失性存储器件包括具有第一区域和第二区域的衬底。 第一栅电极设置在第一区域上。 在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。 第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。 栅极绝缘层介于第二栅电极和衬底之间。 第二栅电极的第一栅电极和上栅极包括相同的材料。

公开(公告)号：US20090250747A1

公开(公告)日：2009-10-08

申请号：US12422862

申请日：2009-04-13

申请人： Chang-Hyun Lee ,  Kyu-Charn Park

发明人： Chang-Hyun Lee ,  Kyu-Charn Park

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

摘要翻译： 非易失性存储器件包括具有第一区域和第二区域的衬底。 第一栅电极设置在第一区域上。 在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。 第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。 栅极绝缘层介于第二栅电极和衬底之间。 第二栅电极的第一栅电极和上栅极包括相同的材料。

公开(公告)号：US07508048B2

公开(公告)日：2009-03-24

申请号：US10758802

申请日：2004-01-15

申请人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

发明人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

IPC分类号： H01L29/00

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543

摘要： Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.

摘要翻译： 提供了制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法。 该方法包括分别在半导体衬底的第一区域和第二区域上形成衬垫绝缘层和初始高电压栅极绝缘层。 初始高压栅绝缘层形成为比焊垫绝缘层厚。 形成穿过焊盘绝缘层并被埋在半导体衬底中的第一隔离层，以限定第一区域中的第一有源区和穿过初始高电压栅极绝缘层并被埋在半导体中的第二隔离层 形成衬底以限定第二区域中的第二有源区。 然后去除焊盘绝缘层以露出第一有源区。 在暴露的第一有源区上形成低压栅极绝缘层。 因此，能够最大限度地减少在去除焊盘绝缘层期间在第一隔离层的边缘区域形成的凹陷区域（凹陷区域）的深度，并且可以防止凹陷区域形成在第二隔离层的边缘区域 。