公开(公告)号：US07879511B2

公开(公告)日：2011-02-01

申请号：US11368634

申请日：2006-03-07

申请人： Chih-Wei Chao

发明人： Chih-Wei Chao

IPC分类号： G03F1/00

CPC分类号： H01L21/02532 ,  H01L21/0268 ,  H01L21/02691 ,  H01L27/1285 ,  H01L27/1296

摘要： A mask used in a sequential lateral solidification process to fabricate a multi-boundary polysilicon. The mask comprises a first portion, a second portion and a third portion. The first and the third portions are translucent to light, and the second portion is opaque. These three portions have the same shape but different sizes. The first portion surrounds the second portion, and the third portion is parallel to both the first and the second portions.

摘要翻译： 用于顺序横向凝固工艺中制造多孔膜的掩模。 掩模包括第一部分，第二部分和第三部分。 第一和第三部分对于光是半透明的，而第二部分是不透明的。 这三个部分具有相同的形状但尺寸不同。 第一部分围绕第二部分，并且第三部分平行于第一部分和第二部分。

公开(公告)号：US20100012970A1

公开(公告)日：2010-01-21

申请号：US12204815

申请日：2008-09-05

申请人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

发明人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L33/20 ,  H01L33/38 ,  H01L33/46

摘要： An LED chip includes a substrate, a semiconductor device layer, a wall structure, and a number of electrodes. The semiconductor device layer is disposed on the substrate and includes a first-type doped semiconductor layer disposed on the substrate, an active layer disposed on a portion of the first-type doped semiconductor layer, and a second-type doped semiconductor layer disposed on the active layer and having a first top surface. The wall structure is disposed on the first-type doped semiconductor layer that is not covered by the active layer and surrounds the active layer. Besides, the wall structure has a second top surface higher than the first top surface of the second-type doped semiconductor layer. Additionally, the electrodes are disposed on and electrically connected with the first-type doped semiconductor layer and the second-type doped semiconductor layer.

摘要翻译： LED芯片包括基板，半导体器件层，壁结构和多个电极。 半导体器件层设置在衬底上，并且包括设置在衬底上的第一掺杂半导体层，设置在第一掺杂半导体层的一部分上的有源层和设置在第一掺杂半导体层上的第二掺杂半导体层 活性层并具有第一顶表面。 壁结构设置在第一型掺杂半导体层上，未被有源层覆盖并包围有源层。 此外，壁结构具有比第二类型掺杂半导体层的第一顶表面高的第二顶表面。 此外，电极设置在第一掺杂半导体层和第二掺杂半导体层上并与之电连接。

公开(公告)号：US07476601B2

公开(公告)日：2009-01-13

申请号：US11202178

申请日：2005-08-12

申请人： Chih-Wei Chao ,  Mao-Yi Chang

发明人： Chih-Wei Chao ,  Mao-Yi Chang

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04

摘要： A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first and second polysilicon regions. The third polysilicon region is formed on the insulating layer and disposed above the gap. When the semiconductor structure is applied to a display panel, a grain boundary of the third polysilicon region in a displaying region and a channel of an active layer intersect at an angle, and the grain boundary of the third polysilicon region in a circuit driving region is substantially parallel to the channel of the active layer.

公开(公告)号：US20080225192A1

公开(公告)日：2008-09-18

申请号：US12019701

申请日：2008-01-25

申请人： Yi-Sheng Cheng ,  Chih-Wei Chao

发明人： Yi-Sheng Cheng ,  Chih-Wei Chao

IPC分类号： G02F1/1343 ,  H01L21/84

CPC分类号： H01L27/124 ,  G02F1/136209 ,  G02F1/136213 ,  G02F2001/136231 ,  H01L27/1255 ,  H01L27/1288

摘要： Five photomasks are used in fabricating the pixel structure of an LCD. In this pixel structure, a metal light-shielding layer is formed under the thin film transistor to reduce photocurrent. Furthermore, a metal conductive wire is used to increase the storage capacity of the storage capacitor.

摘要翻译： 五个光掩模用于制造LCD的像素结构。 在该像素结构中，在薄膜晶体管的下方形成金属遮光层，以减少光电流。 此外，使用金属导线来增加存储电容器的存储容量。

公开(公告)号：US20080203395A1

公开(公告)日：2008-08-28

申请号：US11743676

申请日：2007-05-03

申请人： Chih-Wei Chao ,  Chien-Sen Weng ,  MING-WEI SUN ,  Yi-Wei Chen

发明人： Chih-Wei Chao ,  Chien-Sen Weng ,  MING-WEI SUN ,  Yi-Wei Chen

IPC分类号： H01L29/04 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/78633 ,  H01L29/66757

摘要： A semiconductor device and a method for manufacturing the same are provided. First, a transparent substrate is provided. Next, a light-shielding layer is formed over the transparent substrate and a first buffer layer is formed to cover the light-shielding layer. A semiconductor layer is formed over the first buffer layer. Then, the light-shielding layer, the first buffer layer and the semiconductor layer are patterned to form a laminate pattern. A channel and a source/drain region at two sides of the channel are formed within the semiconductor layer. Then, a gate insulating layer is formed over the transparent substrate to cover the laminate pattern. A gate electrode is formed on the gate insulating layer above the channel.

摘要翻译： 提供半导体器件及其制造方法。 首先，提供透明基板。 接着，在透明基板的上方形成有遮光层，形成第一缓冲层覆盖遮光层。 在第一缓冲层上形成半导体层。 然后，对遮光层，第一缓冲层和半导体层进行图案化以形成层叠图案。 在半导体层内形成沟道两侧的沟道和源/漏区。 然后，在透明基板上形成栅极绝缘层以覆盖叠层图案。 栅极电极形成在通道上方的栅极绝缘层上。

公开(公告)号：US07417279B2

公开(公告)日：2008-08-26

申请号：US11205108

申请日：2005-08-17

申请人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

发明人： Chih-Wei Chao ,  Chin-Wei Hu ,  Chi-Wen Chen

IPC分类号： H01L29/94

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1203

摘要： An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected.

摘要翻译： EEPROM包括基板，形成在基板上的第一半导体层和第二半导体层。 第一半导体层通过沟槽与第二半导体层隔离。 第一源极和第一漏极位于第一半导体层的相对两侧。 在第一半导体层上形成第一电介质层，在第一电介质层上形成第一浮栅。 第二源极和第二漏极位于第二半导体层的两个相对侧。 在第二半导体层上形成第二电介质层，在第二电介质层上形成第二浮栅。 第一浮栅和第二浮栅电连接。

公开(公告)号：US20070052004A1

公开(公告)日：2007-03-08

申请号：US11320061

申请日：2005-12-28

申请人： Chih-Wei Chao ,  Mao-Yi Chang ,  I-Chang Tsao

发明人： Chih-Wei Chao ,  Mao-Yi Chang ,  I-Chang Tsao

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L29/40114 ,  H01L31/0352 ,  H01L31/068 ,  Y02E10/547

摘要： A method of manufacturing nano crystals disclosed herein is applicable to the fabrications of memory device and solar cell. The method of manufacturing nano crystals at least comprises steps of: providing a substrate with a thin film formed thereon, and transforming the thin film into the nano crystals by laser annealing, wherein a thickness of the thin film is equal to or less than about 50 Å, and a wavelength of the laser selected for laser annealing is equal to or less than about 500 nm.

摘要翻译： 本文公开的制造纳米晶体的方法适用于存储器件和太阳能电池的制造。 制造纳米晶体的方法至少包括以下步骤：为基板提供形成在其上的薄膜，并通过激光退火将薄膜转变成纳米晶体，其中薄膜的厚度等于或小于约50 并且激光退火选择的激光的波长等于或小于约500nm。

公开(公告)号：US09577137B2

公开(公告)日：2017-02-21

申请号：US12202647

申请日：2008-09-02

申请人： An-Thung Cho ,  Chih-Wei Chao ,  Chia-Tien Peng ,  Kun-Chih Lin

发明人： An-Thung Cho ,  Chih-Wei Chao ,  Chia-Tien Peng ,  Kun-Chih Lin

IPC分类号： H01L31/04 ,  H01L31/0352 ,  H01L21/28 ,  H01L27/12 ,  H01L31/06 ,  H01L31/10 ,  H01L31/18

CPC分类号： H01L31/1804 ,  G01J1/0247 ,  G01J1/4204 ,  H01L21/28273 ,  H01L27/12 ,  H01L27/1214 ,  H01L31/0352 ,  H01L31/06 ,  H01L31/10 ,  Y02E10/547 ,  Y02P70/521

摘要： One aspect of the present invention relates to a photovoltaic cell. In one embodiment, the photovoltaic cell includes a first conductive layer, an N-doped semiconductor layer formed on the first conductive layer, a first silicon layer formed on the N-doped semiconductor layer, a nanocrystalline silicon (nc-Si) layer formed on a first silicon layer, a second silicon layer formed on the nc-Si layer, a P-doped semiconductor layer on the second silicon layer, and a second conductive layer formed on the P-doped semiconductor layer, where one of the first silicon layer and the second silicon layer is formed of amorphous silicon, and the other of the first silicon layer and the second silicon layer formed of polycrystalline silicon.

摘要翻译： 本发明的一个方面涉及一种光伏电池。 在一个实施例中，光伏电池包括第一导电层，形成在第一导电层上的N掺杂半导体层，形成在N掺杂半导体层上的第一硅层，形成在N掺杂半导体层上的纳米晶硅（nc-Si）层 第一硅层，形成在nc-Si层上的第二硅层，在第二硅层上的P掺杂半导体层，以及形成在P掺杂半导体层上的第二导电层，其中第一硅层 并且所述第二硅层由非晶硅形成，并且所述第一硅层和所述第二硅层中的另一个由多晶硅形成。

公开(公告)号：US08373179B2

公开(公告)日：2013-02-12

申请号：US13159430

申请日：2011-06-14

申请人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

发明人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

IPC分类号： H01L33/00

CPC分类号： H01L33/145 ,  H01L33/387

摘要： A LED chip including a substrate, a semiconductor device layer, a current blocking layer, a current spread layer, a first electrode and a second electrode is provided. The semiconductor device layer is disposed on the substrate. The current blocking layer is disposed on a part of the semiconductor device layer and includes a current blocking segment and a current distribution adjusting segment. The current spread layer is disposed on a part of the semiconductor device layer and covers the current blocking layer. The first electrode is disposed on the current spread layer, wherein a part of the current blocking segment is overlapped with the first electrode. Contours of the current blocking segment and the first electrode are similar figures. Contour of the first electrode and is within contour of the current blocking segment. The current distribution adjusting segment is not overlapped with the first electrode.

摘要翻译： 提供了包括衬底，半导体器件层，电流阻挡层，电流扩散层，第一电极和第二电极的LED芯片。 半导体器件层设置在基板上。 电流阻挡层设置在半导体器件层的一部分上，并且包括电流阻挡段和电流分布调节段。 电流扩展层设置在半导体器件层的一部分上并覆盖电流阻挡层。 第一电极设置在电流扩展层上，其中电流阻挡段的一部分与第一电极重叠。 当前阻挡段和第一电极的轮廓是相似的图。 第一个电极的等高线并且在当前阻挡段的轮廓内。 电流分布调节段不与第一电极重叠。

公开(公告)号：US08329487B2

公开(公告)日：2012-12-11

申请号：US12916642

申请日：2010-11-01

申请人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

发明人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

IPC分类号： H01L33/02

CPC分类号： H01L33/20 ,  H01L33/38 ,  H01L33/46

摘要： In a fabricating method of an LED, a first-type doped semiconductor material layer, a light emitting material layer, and a second-type doped semiconductor material layer are sequentially formed on a substrate. The first-type and second-type doped semiconductor material layers and the light emitting material layer are patterned to form a first-type doped semiconductor layer, an active layer, and a second-type doped semiconductor layer. The active layer is disposed on a portion of the first-type doped semiconductor layer. The second-type doped semiconductor layer is disposed on the active layer and has a first top surface. A wall structure is formed on the first-type doped semiconductor layer that is not covered by the active layer, and the wall structure surrounds the active layer and has a second top surface higher than the first top surface of the second-type doped semiconductor layer. Electrodes are formed on the first-type and second-type doped semiconductor layers.

摘要翻译： 在LED的制造方法中，在衬底上依次形成第一掺杂半导体材料层，发光材料层和第二掺杂半导体材料层。 图案化第一类型和第二类型掺杂半导体材料层和发光材料层以形成第一掺杂半导体层，有源层和第二掺杂半导体层。 有源层设置在第一掺杂半导体层的一部分上。 第二掺杂半导体层设置在有源层上并具有第一顶表面。 在第一型掺杂半导体层上形成壁结构，其不被有源层覆盖，并且壁结构围绕有源层，并且具有比第二类型掺杂半导体层的第一顶表面高的第二顶表面 。 电极形成在第一和第二掺杂半导体层上。