公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US06914320B2

公开(公告)日：2005-07-05

申请号：US10807029

申请日：2004-03-23

申请人： Tze-Chiang Chen ,  Brett H. Engel ,  John A. Fitzsimmons ,  Terence Kane ,  Naftall E. Lustig ,  Ann McDonald ,  Vincent McGahay ,  Soon-Cheon Seo ,  Anthony K. Stamper ,  Yun Yu Wang ,  Erdem Kaltalioglu

发明人： Tze-Chiang Chen ,  Brett H. Engel ,  John A. Fitzsimmons ,  Terence Kane ,  Naftall E. Lustig ,  Ann McDonald ,  Vincent McGahay ,  Soon-Cheon Seo ,  Anthony K. Stamper ,  Yun Yu Wang ,  Erdem Kaltalioglu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

摘要翻译： 公开了一种先进的后端（BEOL）金属化结构。 该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由介电材料形成，优选沉积 通过等离子体增强化学气相沉积（PE CVD）工艺。 还公开了一种用于形成BEOL金属化结构的方法。 本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

公开(公告)号：US20050011442A1

公开(公告)日：2005-01-20

申请号：US10604058

申请日：2003-06-24

申请人： Bomy Chen ,  John Fitzsimmons ,  Vincent McGahay ,  James Ryan ,  Pavel Smetana

发明人： Bomy Chen ,  John Fitzsimmons ,  Vincent McGahay ,  James Ryan ,  Pavel Smetana

IPC分类号： C23C16/44 ,  C23C16/455 ,  H01J37/32 ,  C23C16/00 ,  H05H1/24

CPC分类号： C23C16/45593 ,  C23C16/4412 ,  H01J37/32844 ,  Y02C20/30

摘要： An integrated circuit plasma processing system, apparatus and method for reclaiming material, such as a plasma precursor and potentially useful components among their byproducts, from plasma-enhanced exhaust of a plasma process chamber for subsequent reuse in the chamber. The apparatus provides a recycle feedback loop for a plasma process chamber that provides the high purity materials necessary for microelectronic applications. Since the apparatus is in-situ, no byproducts that are not already present are possible. Accordingly, the apparatus guarantees purity of the recycled material. In addition to cost savings, the invention provides an environmentally friendly plasma process chamber and apparatus with very little production of waste.

摘要翻译： 用于从等离子体增强的等离子体处理室的排气中回收诸如等离子体前体和其副产物中的潜在有用组分的材料的集成电路等离子体处理系统，装置和方法，用于随后在室中重复使用。 该设备为等离子体处理室提供了循环反馈回路，其提供了微电子应用所需的高纯度材料。 由于设备是原位的，所以不可能存在尚未存在的副产物。 因此，该装置保证再循环材料的纯度。 除了节省成本之外，本发明提供了一种环境友好的等离子体处理室和具有很少废物产生的装置。