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1.发明申请DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES 有权用于减少半导体器件中有效介电常数的器件和方法公开(公告)号：US20050167838A1
公开(公告)日：2005-08-04
申请号：US10707996
申请日：2004-01-30
申请人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
发明人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
IPC分类号： H01L21/033 , H01L21/302 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias
摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙
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公开(公告)号：US20080020230A1
公开(公告)日：2008-01-24
申请号：US11865215
申请日：2007-10-01
CPC分类号： H01L23/53238 , H01L23/5226 , H01L2924/0002 , Y10T428/12493 , H01L2924/00
摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.
摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。
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公开(公告)号：US20060027930A1
公开(公告)日：2006-02-09
申请号：US10710828
申请日：2004-08-05
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L23/5226 , H01L2924/0002 , Y10T428/12493 , H01L2924/00
摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.
摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。
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公开(公告)号：US20050266698A1
公开(公告)日：2005-12-01
申请号：US10709747
申请日：2004-05-26
申请人： Edward Cooney , John Fitzsimmons , Jeffrey Gambino , Stephen Luce , Thomas McDevitt , Lee Nicholson , Anthony Stamper
发明人： Edward Cooney , John Fitzsimmons , Jeffrey Gambino , Stephen Luce , Thomas McDevitt , Lee Nicholson , Anthony Stamper
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/311 , H01L21/316 , H01L21/469 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/02107 , H01L21/02203 , H01L21/02337 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31116 , H01L21/31695 , H01L21/76802 , H01L21/76807 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76868
摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.
摘要翻译： 具有闭孔层的方法和结构，用于封闭图案化的多孔低k电介质层中的暴露孔，以及可选地在低k电介质上的反应性衬垫。 第一反应物被吸收或保留在图案化介电层中的暴露孔中，然后将第二反应物引入开口中，使得其进入暴露的孔，同时第一反应物分子同时脱气。 第二反应物与暴露孔的口部区域处的脱气的第一反应物分子原位反应，以形成穿过暴露孔的口部区域的孔闭合层，同时保留每个孔隙的一部分以保持其孔的特性和性质 多孔低k电介质层。 任选地，第一反应物可以被吸附到低k电介质上，使得当将第二反应物引入图案化的电介质开口中时，还在低k电介质上形成反应性衬垫。
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公开(公告)号：US20060027929A1
公开(公告)日：2006-02-09
申请号：US11247818
申请日：2005-10-11
申请人： Edward Cooney , John Fitzsimmons , Jeffrey Gambino , Stephen Luce , Thomas McDevitt , Lee Nicholson , Anthony Stamper
发明人： Edward Cooney , John Fitzsimmons , Jeffrey Gambino , Stephen Luce , Thomas McDevitt , Lee Nicholson , Anthony Stamper
CPC分类号： H01L21/76831 , H01L21/02107 , H01L21/02203 , H01L21/02337 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31116 , H01L21/31695 , H01L21/76802 , H01L21/76807 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76868
摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.
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6.发明申请公开(公告)号：US20050208781A1
公开(公告)日：2005-09-22
申请号：US10708735
申请日：2004-03-22
CPC分类号： H01L23/562 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.
摘要翻译： 形成方法和集成电路器件结构形成，具有与现有裂纹相邻的垂直接口围绕芯片的周边，由此垂直接口控制器件的侧面处理期间产生的裂纹，例如切割，并且在穿透裂纹停止 。 垂直界面由防止裂纹破坏裂纹的材料组成，通过使裂纹偏离穿透裂缝，或通过吸收所产生的裂纹能量来防止裂纹破裂。 或者，垂直界面可以是允许前进裂纹失去足够的能量使得它们不能穿透裂缝停止的材料。 现有的垂直接口可以以多种方式实现，例如释放材料的垂直间隔物，释放材料的垂直沟槽或释放材料的垂直通道。
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公开(公告)号：US20050098605A1
公开(公告)日：2005-05-12
申请号：US10702416
申请日：2003-11-06
IPC分类号： B23K20/00 , H01L23/485 , B23K37/00
CPC分类号： H01L24/85 , B23K20/007 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05083 , H01L2224/05124 , H01L2224/05147 , H01L2224/05609 , H01L2224/05611 , H01L2224/05644 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48463 , H01L2224/48609 , H01L2224/48611 , H01L2224/48644 , H01L2224/48709 , H01L2224/48711 , H01L2224/48744 , H01L2224/85203 , H01L2224/85205 , H01L2224/85359 , H01L2224/85801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/01049 , H01L2924/00 , H01L2924/00015
摘要： A structure and method for low-pressure wirebonding, reducing the propensity of dielectric material to mechanical failure due to wirebond stress. A low temperature alloy on the surface of a bond pad allows alloy bond formation to occur between the wire and the bond pad at reduced bond pressures and reduced thermal and ultrasonic energies. Preferred alloys include Au—Sn and Au—In. The Au—Sn alloy may be formed over the Cu bond pad, incorporated in an aluminum bond pad stack, or deposited on a bond pad having Ni—Au capping of Cu or Al bond pads.
摘要翻译： 一种用于低压引线键合的结构和方法，降低了由于引线键应力导致的介电材料对机械故障的倾向。 接合焊盘表面上的低温合金允许在降低的接合压力和降低的热和超声能量的情况下在导线和接合焊盘之间形成合金结合。 优选的合金包括Au-Sn和Au-In。 Au-Sn合金可以形成在结合在铝焊盘叠层中的Cu焊盘上，或者沉积在具有Cu或Al键合焊盘的Ni-Au封盖的焊盘上。
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8.发明申请INTERLAYER CONNECTOR FOR PREVENTING DELAMINATION OF SEMICONDUCTOR DEVICE AND METHODS OF FORMING SAME 有权用于防止半导体器件分层的层间连接器及其形成方法公开(公告)号：US20050280152A1
公开(公告)日：2005-12-22
申请号：US10710147
申请日：2004-06-22
IPC分类号： H01L21/768 , H01L23/48 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76832 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interlayer connector for preventing delamination of semiconductor layers, and methods of forming the connector are disclosed. The connector includes a first connector head in a first distal layer, a second connector head in a second distal layer and a connector body coupling the first and second connector heads. Each connector head has a dimension greater is size than the connector body such that the layers are securely held together. The interlayer connector may be isolated from current-carrying wiring or provided in the form of a contact via. The interlayer connector provides a mechanical mechanism to prevent layers from delaminating regardless of the materials used. The invention also eliminates the need for white space fill above and below via fill by using the connectors coplanar with the on device wiring.
摘要翻译： 公开了一种用于防止半导体层分层的层间连接器，以及形成连接器的方法。 连接器包括第一远端层中的第一连接器头部，第二远侧层中的第二连接器头部和联接第一和第二连接器头部的连接器主体。 每个连接器头的尺寸大于连接器主体的尺寸，使得这些层牢固地保持在一起。 层间连接器可以与载流布线隔离或以接触通孔的形式提供。 层间连接器提供机械机构，以防止层分层，而不管使用的材料如何。 本发明还通过使用与开启器件布线共面的连接器，消除了通过填充物上下空白填充的需要。
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公开(公告)号：US20050218504A1
公开(公告)日：2005-10-06
申请号：US10708883
申请日：2004-03-30
IPC分类号： H01L21/311 , H01L21/316 , H01L21/768 , H01L23/14 , H01L23/522 , H01L23/532
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02271 , H01L21/31695 , H01L23/5222 , H01L23/5329 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： In an embodiment of the invention, a dielectric material comprises a matrix of a material selected from the group consisting essentially of organic materials, inorganic materials and organo-silicate materials; a plurality of pores dispersed throughout the matrix; and a gas filling the pores. The gas is selected from the group consisting essentially of inert gases, depositing gases, and breakdown suppressing gases. The filled pore dielectric material is suitably used in a damascene wiring layer. In further embodiments, a plasma device comprises an integrated circuit (IC) chip substrate; at least one dielectric layer having a thickness on a surface of the substrate, a cavity formed in the dielectric layer, at least two electrodes disposed in the cavity; and a plasma gas filling the cavity. The plasma device can operate as a light source or as a switch.
摘要翻译： 在本发明的一个实施方案中，电介质材料包括选自基本上由有机材料，无机材料和有机硅酸盐材料组成的组的基体; 分散在整个基质中的多个孔; 和填充孔的气体。 气体选自基本上由惰性气体，沉积气体和击穿抑制气体组成的组。 填充孔介电材料适用于镶嵌布线层。 在另外的实施例中，等离子体器件包括集成电路（IC）芯片衬底; 至少一个介电层，其具有在所述基板的表面上的厚度，在所述介电层中形成的空腔，设置在所述空腔中的至少两个电极; 以及填充空腔的等离子体气体。 等离子体装置可以作为光源或开关操作。
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公开(公告)号：US20050082347A1
公开(公告)日：2005-04-21
申请号：US10688387
申请日：2003-10-17
IPC分类号： B23K20/00 , H01L21/603 , H01L23/485 , B23K31/02
CPC分类号： H01L24/85 , B23K20/004 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05644 , H01L2224/45015 , H01L2224/45111 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45171 , H01L2224/48463 , H01L2224/48644 , H01L2224/48699 , H01L2224/48844 , H01L2224/85045 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85214 , H01L2224/85345 , H01L2224/85365 , H01L2224/85385 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/48744
摘要： A complimentary self-locking wire bond structure and technique is introduced, where the bonding force is focused at the tip of the bond wire and a barb-type construction is utilized to enhance the durability and reduce the insertion forces. The end of wire bond has an “arrowhead” or similar functioning fastener such that the force is focused to a point that pierces the bond pad in a local area. The bond pad may be self-healing, such that the bond pad is made to close over and seal or lock the barb into the underpad layer below the pad, while making electrical contact with the wire bond at the bond pad surface. The bond pad may have a cushioning layer or cavity below it to dampen the piecing force of the pointed barb. A thin metal pad may also be formed over the compliant underpad layer for force absorption.
摘要翻译： 引入互补的自锁线接合结构和技术，其中结合力聚焦在接合线的尖端处，并且使用倒钩型结构来提高耐久性并减小插入力。 引线接合的末端具有“箭头”或类似功能的紧固件，使得该力被聚焦到在局部区域刺穿接合焊盘的点。 接合焊盘可以是自愈合的，使得接合焊盘被封闭并且将倒钩密封或锁定到焊盘下方的垫底层中，同时与接合焊盘表面处的引线接合。 接合垫可以在其下方具有缓冲层或空腔以抑制尖的倒钩的接头力。 也可以在柔性底垫层上方形成薄金属垫，用于力吸收。
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