公开(公告)号：US06191028B1

公开(公告)日：2001-02-20

申请号：US09059751

申请日：1998-04-14

申请人： Yimin Huang ,  Tri-Rung Yew

发明人： Yimin Huang ,  Tri-Rung Yew

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76811

摘要： A method of patterning a dielectric layer. On a substrate having a metal wiring layer formed thereon, a dielectric layer and a masking layer are formed. A cap insulation layer is formed on the masking layer before patterning the dielectric layer. In addition, a dual damasecence process is used for patterning the dielectric layer.

摘要翻译： 图案化介电层的方法。 在其上形成有金属布线层的基板上，形成介电层和掩模层。 在图案化电介质层之前，在掩模层上形成帽绝缘层。 此外，使用双重破坏过程来对介电层进行图案化。

公开(公告)号：US6156648A

公开(公告)日：2000-12-05

申请号：US265207

申请日：1999-03-10

申请人： Yimin Huang

发明人： Yimin Huang

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76843

摘要： A method for fabricating a dual damascene structure. A cap layer and a dielectric layer are formed in sequence over a substrate having a first conductive layer. A trench and a via hole are formed in the dielectric layer. The via hole is aligned under the trench. A barrier spacer is formed on sidewalls of the trench and the via hole. The cap layer exposed by the via hole is removed. A conformal adhesion layer is formed over the substrate. A second conductive layer is formed over the substrate and fills the trench and the via hole. A portion of the second conductive layer and the adhesion layer are removed to expose the dielectric layer.

摘要翻译： 一种制造双镶嵌结构的方法。 在具有第一导电层的衬底上依次形成覆盖层和电介质层。 在电介质层中形成沟槽和通孔。 通孔在沟槽下对齐。 在沟槽和通孔的侧壁上形成阻挡隔离物。 由通孔露出的盖层被去除。 在衬底上形成共形粘附层。 第二导电层形成在衬底上并填充沟槽和通孔。 去除第二导电层和粘附层的一部分以暴露电介质层。

公开(公告)号：US6077769A

公开(公告)日：2000-06-20

申请号：US72311

申请日：1998-05-04

申请人： Yimin Huang ,  Tony Lin ,  Tri-Rung Yew

发明人： Yimin Huang ,  Tony Lin ,  Tri-Rung Yew

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76811

摘要： A method is provided for fabricating a dual damascene structure on a substrate with a first dielectric layer, an etching stop layer, a second dielectric layer, and a hard mask layer formed on it. The first step is to define the hard mask layer in order to form the first hole, which corresponds to the position of the conductive layer exposing the second dielectric layer. Then, an etching process, including an etching step with medium SiO.sub.2 /SiN etching selectivity and an over-etching step with high SiO.sub.2 /SiN etching selectivity, is performed to form the second hole and the third hole. Finally, a glue/barrier layer and a metal layer are filled into the second hole and the third hole, thus accomplishing a dual damascene structure.

摘要翻译： 提供了一种用于在衬底上制造双镶嵌结构的方法，其上形成有第一介电层，蚀刻停止层，第二介电层和硬掩模层。 第一步是定义硬掩模层以形成第一孔，其对应于暴露第二电介质层的导电层的位置。 然后，进行包括具有中等SiO 2 / SiN蚀刻选择性的蚀刻步骤和具有高SiO 2 / SiN蚀刻选择性的过蚀刻步骤的蚀刻工艺，以形成第二孔和第三孔。 最后，将胶/阻挡层和金属层填充到第二孔和第三孔中，从而实现双镶嵌结构。

公开(公告)号：US6025264A

公开(公告)日：2000-02-15

申请号：US52608

申请日：1998-03-31

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun ,  Yimin Huang

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun ,  Yimin Huang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC分类号： H01L21/76843 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

摘要翻译： 一种用于形成阻挡层的方法，包括以下步骤：首先提供其上已经形成有导电层的半导体衬底。 然后，在导电层和半导体衬底上沉积诸如有机低k电介质层的电介质层。 接下来，形成在暴露导电层的电介质层中的开口。 此后，第一阻挡层沉积到开口和周围区域中。 第一阻挡层可以是通过等离子体增强化学气相沉积（PECVD）法，低压化学气相沉积法（LPCVD）法，电子束 蒸发法或溅射法。 最后，在第一阻挡层上形成第二阻挡层。 第二阻挡层可以是钛/氮化钛（Ti / TiN）层，氮化钨（WN）层，钽（Ta）层或氮化钽（TaN）层。

公开(公告)号：US6001733A

公开(公告)日：1999-12-14

申请号：US164856

申请日：1998-10-01

申请人： Yimin Huang ,  Ming-Sheng Yang ,  Tri-Rung Yew

发明人： Yimin Huang ,  Ming-Sheng Yang ,  Tri-Rung Yew

IPC分类号： H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/3212 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/7684 ,  H01L2221/1031

摘要： A method for forming dual damascene is provided. First, a first inter-metal dielectric layer and a stop layer is formed on a substrate, and then a first photoresist pattern including a via hole and a dummy metal line is patterned and the stop layer is etched for forming via hole. Next, a second inter-metal dielectric layer is deposited and then a second photoresist pattern is patterned for forming metal line trench by etching. Afterwards, a glue layer and a metal layer are blanketed and the dual damascene structure is formed by chemical mechanical polishing.

摘要翻译： 提供了一种形成双镶嵌的方法。 首先，在基板上形成第一金属间介电层和停止层，然后对包括通孔和虚拟金属线的第一光致抗蚀剂图案进行图案化，并且对停止层进行蚀刻以形成通孔。 接下来，沉积第二金属间介电层，然后对第二光致抗蚀剂图案进行图案化以通过蚀刻形成金属线沟槽。 然后，胶合层和金属层被覆盖，并通过化学机械抛光形成双镶嵌结构。

公开(公告)号：US10163724B2

公开(公告)日：2018-12-25

申请号：US13409999

申请日：2012-03-01

申请人： Pai-Chieh Wang ,  Yimin Huang

发明人： Pai-Chieh Wang ,  Yimin Huang

IPC分类号： H01L21/8238

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer.

公开(公告)号：US09269833B2

公开(公告)日：2016-02-23

申请号：US13303096

申请日：2011-11-22

申请人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

IPC分类号： H01L29/94 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC分类号： H01L29/94 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20

摘要： Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.

摘要翻译： 替代栅极工艺中混合MOS电容器的方法和装置。 公开了一种方法，其包括图案化栅极电介质层和多晶硅栅极层以在衬底上形成多晶硅栅极区域; 在所述衬底上形成层间电介质层并围绕所述多晶硅栅极区域; 限定多晶硅电阻器区域，每个多晶硅电阻器区域包含多晶硅栅极区域的至少一部分并且不包含多晶硅栅极区域的至少一个其他部分，形成伪栅极区域，去除伪栅极区域和伪栅极区域下方的栅极介电层，以留下 沟渠 并在沟槽中形成高k金属栅极器件。 公开了一种包括高k金属栅极和与高k金属栅极相邻的多晶硅栅极的电容器区域。 公开了另外的混合电容器装置。

公开(公告)号：US08857739B2

公开(公告)日：2014-10-14

申请号：US13323754

申请日：2011-12-12

申请人： Yimin Huang ,  Shaun Sullivan ,  Brian Finstad ,  Alexander Haplau-Colan

发明人： Yimin Huang ,  Shaun Sullivan ,  Brian Finstad ,  Alexander Haplau-Colan

IPC分类号： B05B7/10 ,  F02C1/00 ,  F02G3/00 ,  F23R3/14 ,  F23R3/28 ,  F23R3/46

CPC分类号： F23R3/14 ,  F23R3/283 ,  F23R3/286 ,  F23R3/46

摘要： A combustor for a gas turbine engine is disclosed which is able to operate with high combustion efficiency, and low nitrous oxide emissions during gas turbine operations. The combustor consists of a can-type configuration which combusts fuel premixed with air and delivers the hot gases to a turbine. Fuel is premixed with air through a swirler and is delivered to the combustor with a high degree of swirl motion about a central axis. This swirling mixture of reactants is conveyed downstream through a flow path that expands; the mixture reacts, and establishes an upstream central recirculation flow along the central axis. A cooling assembly is located on the swirler co-linear with the central axis in which cooler air is conveyed into the prechamber between the recirculation flow and the swirler surface.

摘要翻译： 公开了一种用于燃气涡轮发动机的燃烧器，其能够在燃气轮机操作期间以高燃烧效率和低氧化亚氮排放进行操作。 燃烧器由罐型构成，其燃烧与空气预混合的燃料并将热气体输送到涡轮机。 燃料通过旋流器与空气预混合并且以围绕中心轴线的高度漩涡运动输送到燃烧器。 反应物的这种旋转混合物通过膨胀的流动路径向下游传送; 混合物反应，并建立沿中心轴的上游中央再循环流。 冷却组件位于与中心轴线共线的旋流器上，其中较冷的空气被输送到再循环流和旋流器表面之间的预燃室中。

公开(公告)号：US20050263876A1

公开(公告)日：2005-12-01

申请号：US11196038

申请日：2005-08-02

申请人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/768 ,  H01L23/12 ,  H01L23/532

CPC分类号： H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

摘要翻译： 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

公开(公告)号：US06794752B2

公开(公告)日：2004-09-21

申请号：US09864055

申请日：2001-05-23

申请人： Ellis Lee ,  Yimin Huang ,  Tri-Rung Yew

发明人： Ellis Lee ,  Yimin Huang ,  Tri-Rung Yew

IPC分类号： H01L2348

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.

摘要翻译： 焊盘结构在铜层上具有钝化层，其具有用于暴露铜层的一部分的焊盘窗口，与焊盘窗口的轮廓保形的阻挡层和位于焊盘窗口中的铝焊盘。 金属层可以是铝，铝合金或铝主导层，用于在铜层和接合线之间提供更好的粘合性能。