公开(公告)号：US10163724B2

公开(公告)日：2018-12-25

申请号：US13409999

申请日：2012-03-01

Applicant: Pai-Chieh Wang ,  Yimin Huang

Inventor： Pai-Chieh Wang ,  Yimin Huang

IPC: H01L21/8238

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer.

公开(公告)号：US09269833B2

公开(公告)日：2016-02-23

申请号：US13303096

申请日：2011-11-22

Applicant: Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

Inventor： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

IPC: H01L29/94 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L29/94 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20

Abstract: Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.

Abstract translation: 替代栅极工艺中混合MOS电容器的方法和装置。 公开了一种方法，其包括图案化栅极电介质层和多晶硅栅极层以在衬底上形成多晶硅栅极区域; 在所述衬底上形成层间电介质层并围绕所述多晶硅栅极区域; 限定多晶硅电阻器区域，每个多晶硅电阻器区域包含多晶硅栅极区域的至少一部分并且不包含多晶硅栅极区域的至少一个其他部分，形成伪栅极区域，去除伪栅极区域和伪栅极区域下方的栅极介电层，以留下 沟渠 并在沟槽中形成高k金属栅极器件。 公开了一种包括高k金属栅极和与高k金属栅极相邻的多晶硅栅极的电容器区域。 公开了另外的混合电容器装置。

公开(公告)号：US09412883B2

公开(公告)日：2016-08-09

申请号：US13303083

申请日：2011-11-22

Applicant: Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

Inventor： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC: H01L29/94 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L21/822 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20 ,  H01L29/401 ,  H01L29/94

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract translation: 替代栅极工艺中多晶硅MOS电容器的方法和装置。 一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。 公开了通过该方法制造的装置。

公开(公告)号：US20130126955A1

公开(公告)日：2013-05-23

申请号：US13303096

申请日：2011-11-22

Applicant: Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

Inventor： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L29/94 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20

Abstract: Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.

Abstract translation: 替代栅极工艺中混合MOS电容器的方法和装置。 公开了一种方法，其包括图案化栅极电介质层和多晶硅栅极层以在衬底上形成多晶硅栅极区域; 在所述衬底上形成层间电介质层并围绕所述多晶硅栅极区域; 限定多晶硅电阻器区域，每个多晶硅电阻器区域包含多晶硅栅极区域的至少一部分并且不包含多晶硅栅极区域的至少一个其他部分，形成伪栅极区域，去除伪栅极区域和伪栅极区域下方的栅极介电层，以留下 沟渠 并在沟槽中形成高k金属栅极器件。 公开了一种包括高k金属栅极和与高k金属栅极相邻的多晶硅栅极的电容器区域。 公开了另外的混合电容器装置。

公开(公告)号：US20130126953A1

公开(公告)日：2013-05-23

申请号：US13303083

申请日：2011-11-22

Applicant: Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

Inventor： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L21/822 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20 ,  H01L29/401 ,  H01L29/94

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract translation: 替代栅极工艺中多晶硅MOS电容器的方法和装置。 一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。 公开了通过该方法制造的装置。

公开(公告)号：US20120091539A1

公开(公告)日：2012-04-19

申请号：US12905579

申请日：2010-10-15

Applicant: Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

Inventor： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/165 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.

Abstract translation: 描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。 有源区域具有与隔离区域相接合的第一边缘。 形成在半导体衬底上的栅极结构。 间隔元件邻接栅极结构并覆盖在第一边缘上。 在一个实施例中，隔离区域是STI结构。 可以在间隔物附近形成外延区域。 在实施例中，该外延区域是无面的。

公开(公告)号：US06987057B2

公开(公告)日：2006-01-17

申请号：US10229443

申请日：2002-08-27

Applicant: Ellis Lee ,  Yimin Huang ,  Tri-Rung Yew

Inventor： Ellis Lee ,  Yimin Huang ,  Tri-Rung Yew

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.

Abstract translation: 焊盘结构在铜层上具有钝化层，该钝化层具有用于暴露铜层的一部分的焊盘窗口，与焊盘窗口的轮廓一致的阻挡层和位于焊盘窗口中的铝焊盘。 金属层可以是铝，铝合金或铝主导层，用于在铜层和接合线之间提供更好的粘合性能。

公开(公告)号：US06593223B1

公开(公告)日：2003-07-15

申请号：US09524720

申请日：2000-03-14

Applicant: Yimin Huang ,  Tri-Rung Yew

Inventor： Yimin Huang ,  Tri-Rung Yew

IPC: H01L214763

CPC classification number: H01L21/76829 ,  H01L21/76807

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

公开(公告)号：US06372621B1

公开(公告)日：2002-04-16

申请号：US09293963

申请日：1999-04-19

Applicant: Hermen Liu ,  Yimin Huang

Inventor： Hermen Liu ,  Yimin Huang

IPC: H01L2144

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/48463 ,  H01L2924/0001 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: The present invention provides a method of forming a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The method comprises forming a first dielectric layer at a predetermined area on the surface of the semiconductor chip, forming a second dielectric layer on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and forming the bonding pad on the first dielectric layer.

Abstract translation: 本发明提供了一种在半导体芯片上形成接合焊盘的方法，从而避免了在封装过程中的互连期间剥离焊盘。 焊盘用于将半导体芯片中的集成电路与外部电路电连接。 该方法包括在半导体芯片的表面上的预定区域形成第一电介质层，在第一电介质层比第二电介质层硬的预定区域外的半导体芯片的表面上形成第二电介质层，以及 在第一电介质层上形成接合焊盘。

公开(公告)号：US06211068B1

公开(公告)日：2001-04-03

申请号：US09318228

申请日：1999-05-25

Applicant: Yimin Huang

Inventor： Yimin Huang

IPC: H01L214763

CPC classification number: H01L21/76808 ,  H01L21/76804

Abstract: A dual damascene process for producing interconnects. The dual damascene process includes forming an etching stop layer over a substrate having a conductive layer therein, and forming an inter-layer dielectric layer over the etching stop layer. A mask layer is formed over the dielectric layer. The mask layer and the inter-layer dielectric layer are patterned to form an opening that expose a portion of the etching stop layer. The opening is formed above the conductive layer. Photoresist material is deposited over the mask layer and into the opening. The photoresist layer and the mask layer are patterned, and the photoresist material inside the opening is turned into a photoresist plug at the same time. A top layer of the photoresist plug is removed. Using the patterned photoresist layer and the mask layer as a mask, an anisotropic etching step is carried out to form a plurality of trenches inside the inter-layer dielectric layer. These trenches overlap with the opening. Metal is finally deposited into the opening and the trenches to complete the dual damascene process.

Abstract translation: 用于生产互连的双镶嵌工艺。 双镶嵌工艺包括在其上具有导电层的衬底上形成蚀刻停止层，并在蚀刻停止层上形成层间电介质层。 在电介质层上形成掩模层。 掩模层和层间电介质层被图案化以形成露出蚀刻停止层的一部分的开口。 开口形成在导电层的上方。 光刻胶材料沉积在掩模层上并进入开口。 光致抗蚀剂层和掩模层被图案化，并且开口内部的光致抗蚀剂材料同时变成光致抗蚀剂插塞。 去除光致抗蚀剂插塞的顶层。 使用图案化的光致抗蚀剂层和掩模层作为掩模，进行各向异性蚀刻步骤以在层间电介质层内部形成多个沟槽。 这些沟槽与开口重叠。 金属最终沉积到开口和沟槽中以完成双镶嵌工艺。