公开(公告)号：US20130326184A1

公开(公告)日：2013-12-05

申请号：US13584393

申请日：2012-08-13

申请人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

发明人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

IPC分类号： G06F12/00

CPC分类号： G11C7/1072 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104

摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.

摘要翻译： 存储装置包括主机装置和从装置。 主机设备存储验证数据。 从设备包括存储器单元，控制单元和逻辑单元。 控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。 逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。 前导码数据和存储数据根据内部时钟信号发送。 主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

公开(公告)号：US20120262987A1

公开(公告)日：2012-10-18

申请号：US13308266

申请日：2011-11-30

申请人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

发明人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC分类号： G11C16/10

CPC分类号： G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

摘要翻译： 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

公开(公告)号：US08264900B2

公开(公告)日：2012-09-11

申请号：US13300141

申请日：2011-11-18

申请人： Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C16/28

摘要： Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.

摘要翻译： 通过使用扭曲的数据线和差分感测放大器来减轻耦合到相邻数据线的非易失性存储器中的数据线上的过度擦除感应噪声。 耦合到数据线中的噪声由耦合到参考数据线中的相似噪声补偿并在差分感测放大器中被消除。

公开(公告)号：US07965551B2

公开(公告)日：2011-06-21

申请号：US11703115

申请日：2007-02-07

申请人： Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C7/18 ,  G11C7/02

摘要： A method for metal bit line arrangement is applied to a virtual ground array memory having memory cell blocks. Each memory cell block has memory cells and m metal bit lines, wherein m is a positive integer. The method includes the following steps. First, one of the memory cells is selected as a target memory cell. When the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is a drain metal bit line, and the metal bit line electrically connected to a source is a source metal bit line. Next, a classification of whether the other metal bit lines are charged up when the target memory cell is being read is made. Thereafter, the m metal bit lines are arranged such that charged up metal bit lines are not adjacent to the source metal bit line.

摘要翻译： 一种用于金属位线布置的方法被应用于具有存储单元块的虚拟地阵列存储器。 每个存储单元块具有存储单元和m个金属位线，其中m是正整数。 该方法包括以下步骤。 首先，选择一个存储单元作为目标存储单元。 当读出目标存储单元时，与目标存储单元的漏极电连接的金属位线是漏极金属位线，与源极电连接的金属位线是源极金属位线。 接着，对目标存储单元进行读取时，分类其他金属位线是否被充电。 此后，m个金属位线布置成使得带电的金属位线不与源极金属位线相邻。

公开(公告)号：US07652512B2

公开(公告)日：2010-01-26

申请号：US12027285

申请日：2008-02-07

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： H03L7/00

CPC分类号： H03K5/135 ,  H03K5/06 ,  H03K2005/00195

摘要： A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.

摘要翻译： 提供了应用在SMD块中的时钟同步电路。 时钟同步电路包括多个时钟同步单元级。 时钟同步电路可以通过使用时钟同步单元的每一级中的前向延迟单元，反射镜控制单元或后向延迟单元的新颖的电路设计来实现时钟同步的目的，或者通过使用短脉冲发生电路来产生 用于触发前级延迟单元各级的输出时钟的短脉冲。

公开(公告)号：US07639533B2

公开(公告)日：2009-12-29

申请号：US12028405

申请日：2008-02-08

申请人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C11/03

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage.

摘要翻译： 用于编程本文所述的多个多电平存储器单元的方法包括迭代地改变施加到第一存储器单元的偏置电压，以将第一存储器单元编程为第一阈值状态，以及检测第一单元何时达到预定阈值电压。 记录在达到预定阈值电压时施加到第一存储单元的偏置电压。 通过对作为记录的偏置电压的函数的第二存储器单元施加初始偏置电压将第二存储单元编程为第二阈值状态。

公开(公告)号：US07626867B2

公开(公告)日：2009-12-01

申请号：US12174115

申请日：2008-07-16

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C11/5671

摘要： A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively, wherein each of the 2n level corresponds to a storage status of n bits, and most significant bits of the storage statuses which level 0 to level 2n/2−1 correspond to are different from most significant bits of the storage statuses which level 2n/2 to level 2n−1 correspond to. Next, a target data is divided into n portions and the divided target data is written into n temporary memories respectively. Then, n bits of the target data are written into the multi-level cell. Each of the n bits data is collected from each of the n temporary memories.

摘要翻译： 提供了访问存储器的方法。 存储器包括许多多级单元，每个单元具有至少一个能存储2n位的存储器，n是正整数。 访问存储器的方法包括以下步骤：首先，将存储器的阈值电压分别定义为2n级，其中2n级中的每一级对应于n位的存储状态，存储状态的最高有效位为0级 等级2n / 2-1对应于不同于2n / 2到2n-1级对应的存储状态的最高有效位。 接下来，目标数据被分成n个部分，分割的目标数据被分别写入n个临时存储器。 然后，将目标数据的n位写入多级单元。 从n个临时存储器中的每一个收集n位数据中的每一个。

公开(公告)号：US07613049B2

公开(公告)日：2009-11-03

申请号：US11969856

申请日：2008-01-04

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

摘要翻译： 一种用于在包括串行外设接口存储器件的集成电路中读取的双I / O数据的方法。 在一个实施例中，存储器件包括时钟信号，多个引脚和配置寄存器。 在一个实施例中，配置寄存器包括等待周期计数。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时向存储器件发送读取地址。 在一个实施例中，读地址至少包括第一地址位和第二地址位，第一地址位使用第一输入/输出引脚发送，第二地址位使用第二输入/输出引脚发送。 该方法包括访问与该地址相关联的数据的存储设备，并等待与等待周期计数相关联的预定数量的时钟周期。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时从存储器件传送数据。

公开(公告)号：US20090059668A1

公开(公告)日：2009-03-05

申请号：US11892979

申请日：2007-08-29

申请人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0491

摘要： A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails.

公开(公告)号：US07499335B2

公开(公告)日：2009-03-03

申请号：US11703916

申请日：2007-02-07

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/107 ,  G11C16/16 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.

摘要翻译： 在具有多个存储单元的非易失性存储器中公开了一种用于执行擦除操作的方法。 至少一个存储器单元被编程为在编程之前具有第一区域中的阈值电压电平，并且在编程之后，存储器单元在第二区域中具有阈值电压电平，其中第二区域的阈值电压高于第一区域。 擦除操作实现了可以将负电荷载流子或电子注入到存储单元中的存储器位的编程，而不是使用将热空穴注入存储单元的常规技术。 这可以避免热空穴注入引起的室温漂移和电荷损失。