公开(公告)号：US5907782A

公开(公告)日：1999-05-25

申请号：US134885

申请日：1998-08-15

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91 ,  H01L28/55 ,  H01L28/92

Abstract: The present invention is a method of manufacturing a high density capacitor for use in semiconductor memories. High etching selectivity between BPSG (borophosphosilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a capacitor with a plurality of horizontal fins. First, a nitride layer is formed on a semiconductor substrate. A stacked layer consists of BPSG and silicon oxide formed on the nitride layer. Then a contact hole is formed in the stacked layer and the nitride layer. A highly selective etching is then used to etch the BPSG sublayers of the stacked layer. Next, a first polysilicon layer is formed in the contact hole and the stacked layer, subsequently, a dielectric layer is formed on the first polysilicon layer. Then, undoped hemispherical-grain silicon (HSG--Si) is formed on the dielectric layer. Next, a portion of the dielectric layer is etched using the HSG--Si layer as a hard mask to expose a portion of the first polysilicon layer. A second polysilicon layer is formed on the HSG--Si layer and the exposed first polysilicon layer. An etching back or CMP is used for planarization. Then photolithography and etching process is used to define the storage node. Next the stacked layer is removed by BOE solution. A dielectric film is then formed along the surface of the first and second polysilicon layer. Finally, a third polysilicon layer is formed on the dielectric film. Thus, a capacitor with multiple horizontal fins and vertical pillars is formed.

Abstract translation: 本发明是制造用于半导体存储器的高密度电容器的方法。 使用BPSG（硼磷硅酸玻璃）和CVD氧化物（化学气相沉积氧化物）之间的高蚀刻选择性来制造具有多个水平翅片的电容器。 首先，在半导体衬底上形成氮化物层。 堆叠层由形成在氮化物层上的BPSG和氧化硅组成。 然后在堆叠层和氮化物层中形成接触孔。 然后使用高选择性蚀刻来蚀刻堆叠层的BPSG子层。 接下来，在接触孔和堆叠层中形成第一多晶硅层，随后在第一多晶硅层上形成介电层。 然后，在电介质层上形成未掺杂的半球形硅（HSG-Si）。 接下来，使用HSG-Si层作为硬掩模蚀刻介电层的一部分，以暴露第一多晶硅层的一部分。 在HSG-Si层和暴露的第一多晶硅层上形成第二多晶硅层。 蚀刻背面或CMP用于平坦化。 然后使用光刻和蚀刻工艺来定义存储节点。 接下来，堆叠层由BOE溶液除去。 然后沿着第一和第二多晶硅层的表面形成电介质膜。 最后，在电介质膜上形成第三多晶硅层。 因此，形成具有多个水平翅片和垂直柱的电容器。

公开(公告)号：US5899715A

公开(公告)日：1999-05-04

申请号：US23453

申请日：1998-02-13

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A new method for the manufacturing of a capacitor for a DRAM is disclosed herein. The method for manufacturing a capacitor on a semiconductor wafer including the following steps. Firstly, sequentially forming a first dielectric layer, a first conductive layer, a second dielectric layer and a third dielectric layer formed on the semiconductor wafer. Secondary, the third dielectric layer and a portion of the second dielectric layer are etched. The portion of the second dielectric layer is isotropically etched to form a hemispherical cavity. Next, the second dielectric layer, the first conductive layer and the first dielectric layer is etched sequentially to form a hole in contact with a portion of the semiconductor wafer by using the third dielectric layer as a mask. Subsequently, the third dielectric layer is removed when etching the first dielectric layer. Afterword, a second conductive layer is formed on the second dielectric layer and in the hole. Next, a pattern for an underlying electrode is formed by anisotropically etching a portion of the second conductive layer, the second dielectric layer and the first conductive layer. Successively, the first dielectric layer is isotropically etched, and a fourth dielectric layer is formed on the underlying electrode. Finally, a third conductive layer is formed on the fourth dielectric layer to form an upperlying electrode of the capacitor.

Abstract translation: 这里公开了用于制造用于DRAM的电容器的新方法。 包括以下步骤在半导体晶片上制造电容器的方法。 首先，依次形成在半导体晶片上形成的第一电介质层，第一导电层，第二电介质层和第三电介质层。 次级，第三介电层和第二介电层的一部分被蚀刻。 第二介电层的部分被各向同性地蚀刻以形成半球形腔。 接下来，通过使用第三介电层作为掩模，依次蚀刻第二电介质层，第一导电层和第一电介质层，以形成与半导体晶片的一部分接触的孔。 随后，当蚀刻第一介电层时，去除第三电介质层。 在第二介电层和孔中形成第二导电层。 接下来，通过各向异性蚀刻第二导电层，第二介电层和第一导电层的一部分来形成底层电极的图案。 接着，第一介电层被各向同性地蚀刻，并且在下面的电极上形成第四电介质层。 最后，在第四电介质层上形成第三导电层以形成电容器的上电极。

公开(公告)号：US5895244A

公开(公告)日：1999-04-20

申请号：US4449

申请日：1998-01-08

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28052 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/66545

Abstract: The method of the present invention is a method of forming a gate oxide layer on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a silicon nitride layer is formed over the undoped polysilicon layer. A doped polysilicon layer is formed over the silicon nitride layer. Next, the doped polysilicon layer is patterned to define a gate region. A thermal oxidation is performed on the patterned doped polysilicon gate region to oxidize a portion of the patterned doped polysilicon layer into a thermal oxide film. The thermal oxide film is removed by an etching process. A portion of the first dielectric layer is etched by using the residual doped polysilicon layer as a mask. The undoped polysilicon layer is etched by using the residual doped polysilicon layer and the residual first dielectric layer as a mask. Then, a PSG layer is deposited over the residual nitride layer and the substrate to serve as an ion diffusion source. Subsequently, the PSG layer is etched back to form side-wall spacers. A noble or refractory metal layer is deposited on all areas. Next, a high dose arsenic or phosphorus ion is implanted through the substrate to form first doped regions to serve as source and drain regions of the transistor. Finally, the two-step RTP annealing process is used to form a self-aligned silicided contact nMOSFET.

Abstract translation: 本发明的方法是在基板上形成栅氧化层的方法。 在栅极氧化物层上方形成未掺杂的多晶硅层。 然后，在未掺杂的多晶硅层上形成氮化硅层。 在氮化硅层上形成掺杂多晶硅层。 接下来，将掺杂多晶硅层图案化以限定栅极区域。 在图案化的掺杂多晶硅栅极区域上进行热氧化，以将图案化的掺杂多晶硅层的一部分氧化成热氧化膜。 通过蚀刻工艺除去热氧化膜。 通过使用残余掺杂多晶硅层作为掩模来蚀刻第一介电层的一部分。 通过使用残余掺杂多晶硅层和残留的第一介电层作为掩模来蚀刻未掺杂的多晶硅层。 然后，在剩余氮化物层和衬底上沉积PSG层以用作离子扩散源。 随后，将PSG层回蚀刻形成侧壁间隔物。 高贵或难熔金属层沉积在所有区域上。 接下来，通过衬底注入高剂量的砷或磷离子，以形成用作晶体管的源极和漏极区域的第一掺杂区域。 最后，使用两步RTP退火工艺来形成自对准硅化物接触nMOSFET。

公开(公告)号：US5885873A

公开(公告)日：1999-03-23

申请号：US63211

申请日：1998-04-20

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8234 ,  H01L21/8246 ,  H01L27/112 ,  H01L21/8236

CPC classification number: H01L27/11246 ,  H01L21/823418 ,  H01L27/112

Abstract: The present invention includes forming a thin oxide layer and a polysilicon layer on a substrate. A thin silicon nitride layer is then formed on the polysilicon layer. An etching is performed to etch back the silicon nitride layer and the polysilicon layer on a NMOS cell region. Next, a blanket ion implantation is carried out to form lightly doped drain regions. A coding oxide layer is formed on the NMOS cell region. Then, the silicon nitride layer is stripped. A second polysilicon layer is successively deposited over the substrate. The polysilicon layer, the gate oxide layer and the coding oxide layer are patterned to form the gate structures. A second ion implantation is used to implant ions to form LDD regions. Side wall spacers are then formed on the side walls of the gate structures. Next, a third ion implantation is then carried out to dope ions into the substrate thereby forming source and drain regions. A high temperature thermal anneal is performed to activate the dopant.

Abstract translation: 本发明包括在基板上形成薄氧化物层和多晶硅层。 然后在多晶硅层上形成薄的氮化硅层。 执行蚀刻以在NMOS单元区域上回蚀刻氮化硅层和多晶硅层。 接下来，进行覆盖式离子注入以形成轻掺杂漏极区。 编码氧化层形成在NMOS单元区域上。 然后，剥离氮化硅层。 第二多晶硅层依次沉积在衬底上。 将多晶硅层，栅极氧化物层和编码氧化物层图案化以形成栅极结构。 使用第二离子注入来注入离子以形成LDD区。 然后在门结构的侧壁上形成侧壁间隔物。 接下来，进行第三离子注入以将离子掺杂到衬底中，从而形成源区和漏区。 执行高温热退火以激活掺杂剂。

公开(公告)号：US5877048A

公开(公告)日：1999-03-02

申请号：US46331

申请日：1998-03-23

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/76

CPC classification number: H01L21/8238 ,  H01L21/84 ,  H01L27/1203

Abstract: The present invention discloses a method for manufacturing 3-D transistors with high electrostatic discharge (ESD) reliability. Pad oxide layers are on a silicon substrate and a thick field oxide is on the silicon substrate between the pad oxide layer. An oxygen amorphized region is formed in the substrate by using an ion implantation having oxygen ions as dopants and the field oxide as a hard mask. A high-temperature thermal annealing is implemented to convert the oxygen amorphized region into an oxygen implant-induced oxide regions. Then, the pad oxide layers and the field oxide are removed to form a field oxide region on the substrate and silicon islands on the oxygen implant-induced oxide regions. A thin gate oxide is deposited on the surface of the substrate and the silicon islands to seal the silicon islands. Finally, PMOSFETs are formed on the silicon islands and bulk NMOSFET buffers are formed on the field oxide region of the substrate.

Abstract translation: 本发明公开了一种制造具有高静电放电（ESD）可靠性的3-D晶体管的方法。 焊盘氧化物层在硅衬底上，厚氧化物层位于衬底氧化物层之间的硅衬底上。 通过使用具有氧离子作为掺杂剂的离子注入和场氧化物作为硬掩模，在衬底中形成氧非晶形区域。 实施高温热退火以将氧非晶化区域转化为氧注入物诱导的氧化物区域。 然后，去除衬垫氧化物层和场氧化物以在衬底上形成场氧化物区域，并在氧注入物诱导的氧化物区域上形成硅岛。 在衬底和硅岛的表面上沉积薄栅氧化物以密封硅岛。 最后，在硅岛上形成PMOSFET，并且在衬底的场氧化物区域上形成体NMOSFET缓冲器。

公开(公告)号：US5814549A

公开(公告)日：1998-09-29

申请号：US746858

申请日：1996-11-18

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/92 ,  H01L28/55

Abstract: A method of manufacturing porous-Si capacitors for use in semiconductor memories is disclosed herein. The present invention includes a SOG layer as an etching mask to etch a polysilicon layer to form a porous-Si structure. The etching process is performed to etch a portion of the first conductive layer and to etch away the remaining HSG-Si. Next, the residure SOG layer is removed to define a porous-Si bottom storage. Utilizing the porous-Si structure, the present invention can be used to increase the surface area of the capacitor.

Abstract translation: 本文公开了制造用于半导体存储器的多孔硅电容器的方法。 本发明包括SOG层作为蚀刻掩模，以蚀刻多晶硅层以形成多孔Si结构。 执行蚀刻工艺以蚀刻第一导电层的一部分并蚀刻掉剩余的HSG-Si。 接下来，去除残留的SOG层以限定多孔Si底部储存器。 利用多孔Si结构，本发明可用于增加电容器的表面积。

公开(公告)号：US5811342A

公开(公告)日：1998-09-22

申请号：US13691

申请日：1998-01-26

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/266 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/266 ,  H01L29/6653 ,  H01L29/7833 ,  Y10S148/106 ,  Y10S148/161 ,  Y10S257/90 ,  Y10S438/965

Abstract: A method for forming a semiconductor device with a graded lightly-doped drain (LDD) structure is disclosed. The method includes providing a semiconductor substrate (10) having a gate region (14 and 16) thereon, followed by forming a pad layer (18) on the substrate and the gate region. Next, ions are implanted into the substrate, and a spacer (22) is formed on sidewalls of the gate region, wherein the first spacer has a concave surface inwards on a surface of the first spacer. Finally, ions are further implanted into the substrate using the gate region and the spacer as a mask, thereby forming a graded doping profile (20) in the substrate.

Abstract translation: 公开了一种形成具有渐变轻掺杂漏极（LDD）结构的半导体器件的方法。 该方法包括提供其上具有栅极区域（14和16）的半导体衬底（10），然后在衬底和栅极区域上形成焊盘层（18）。 接下来，将离子注入到衬底中，并且在栅极区域的侧壁上形成间隔物（22），其中第一间隔物在第一间隔物的表面上具有凹面。 最后，使用栅极区域和间隔物作为掩模将离子进一步注入到衬底中，从而在衬底中形成渐变的掺杂分布（20）。

公开(公告)号：US5736446A

公开(公告)日：1998-04-07

申请号：US859753

申请日：1997-05-21

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66492 ,  H01L21/2254 ,  H01L21/2256 ,  H01L21/823468 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/1083 ,  Y10S438/96

Abstract: A method of fabricating a MOS device having a gate-side air-gap structure is provided. A nitride spacer for reserving space of the air gap is formed on the substrate adjacent to the gate structure. An amorphous silicon spacer for forming the sidewall spacer and sealing the air gap is formed adjacent to the nitride spacer. The upper portion of the amorphous silicon spacer is heavily doped during the source/drain implantation. After removing the nitride spacer the doped amorphous silicon spacer is oxidized by a wet oxidation process to form a doped oxide spacer. The growing doped oxide spacer will seal the hole for the nitride spacer resulting from the heavily doped upper portion having a higher oxidation rate than that of other portions. Dopants implanted in the amorphous silicon spacer migrate into the substrate and extended ultra-shallow doped regions are formed that reduce the series resistance of the LDD structure.

Abstract translation: 提供一种制造具有栅极侧气隙结构的MOS器件的方法。 在与栅极结构相邻的衬底上形成用于保留空隙的空间的氮化物间隔物。 在氮化物间隔物附近形成用于形成侧壁间隔物并密封气隙的非晶硅间隔物。 在源极/漏极注入期间，非晶硅间隔物的上部被重掺杂。 在去除氮化物间隔物之后，通过湿氧化工艺氧化掺杂的非晶硅间隔物以形成掺杂氧化物间隔物。 生长的掺杂氧化物间隔物将密封由重掺杂的上部产生的氮化物间隔物的孔，其氧化速率高于其它部分的氧化速率。 注入到非晶硅间隔物中的掺杂剂迁移到衬底中，并且形成延伸的超浅掺杂区域，其减小LDD结构的串联电阻。

公开(公告)号：US5670397A

公开(公告)日：1997-09-23

申请号：US783754

申请日：1997-01-16

Applicant: Yih-Jau Chang ,  Shye-Lin Wu

Inventor： Yih-Jau Chang ,  Shye-Lin Wu

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A CMOS device with buried contacts is formed using a polysilicon stack layer and twin-well and liquid phase deposition (LPD) processes. A gate oxide layer and a first polysilicon layer are formed on a substrate. Then the gate oxide and first polysilicon layer are etched to form gate structures. A polysilicon stack layer is formed on the gate structures. The polysilicon stack layer and the first polysilicon layer are anisotropically dry etched, forming first trenches that expose portions of the gate oxide and portions of the substrate defining S/D regions for a NMOSFET. A NMOS lightly doped drain (LDD) with halo doping profile is implanted. A first LPD oxide is selectively formed in the first trenches. Subsequently, a first heavy ion implantation is performed into the polysilicon stack layer for forming the source, drain, gate and buried contacts of the NMOSFET. Trenches are formed in the polysilicon stack layer and first polysilicon layer to define S/D regions and buried contacts for a PMOSFET. A PMOS LDD with halo doping profile is implanted. A second LPD oxide is selectively formed in the second trenches. A second heavy ion implantation is performed into the polysilicon stack layer to form the source, drain, gate and buried contacts of the PMOSFET. A thermal treatment is used to condense the LPD oxide and to activate the S/D implants and diffuse the heavy implants from the polysilicon stack layer into the substrate to form the buried contacts.

Abstract translation: 具有埋入触点的CMOS器件使用多晶硅堆叠层和双阱和液相沉积（LPD）工艺形成。 在基板上形成栅极氧化层和第一多晶硅层。 然后蚀刻栅极氧化物和第一多晶硅层以形成栅极结构。 在栅极结构上形成多晶硅堆叠层。 多晶硅堆叠层和第一多晶硅层被各向异性地干蚀刻，形成第一沟槽，其暴露出栅极氧化物的部分和限定用于NMOSFET的S / D区域的衬底的部分。 注入具有晕圈掺杂分布的NMOS轻掺杂漏极（LDD）。 在第一沟槽中选择性地形成第一LPD氧化物。 随后，对多晶硅叠层进行第一次重离子注入，以形成NMOSFET的源极，漏极，栅极和埋入触点。 沟槽形成在多晶硅堆叠层和第一多晶硅层中以限定用于PMOSFET的S / D区域和埋入触点。 植入具有晕圈掺杂分布的PMOS LDD。 在第二沟槽中选择性地形成第二LPD氧化物。 对多晶硅堆叠层进行第二次重离子注入以形成PMOSFET的源极，漏极，栅极和埋入触点。 热处理用于冷凝LPD氧化物并激活S / D植入物，并将重掺杂物从多晶硅堆叠层扩散到衬底中以形成掩埋触点。

公开(公告)号：US07078780B2

公开(公告)日：2006-07-18

申请号：US10826304

申请日：2004-04-19

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L31/62

CPC classification number: H01L29/0623 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/8725

Abstract: A power Schottky rectifier device having a plurality of first trenches filled in with an un-doped polycrystalline silicon layer and each first trenches also has a p-region beneath the bottom of said first trenches to block out reverse current while a reverse biased is applied and to reduce minority carrier while forward biased is applied. Thus, the power Schottky rectifier device can provide first fast switch speed. The power Schottky rectifier device is formed with termination region at an outer portion of the substrate. The manufacture method is also provided.

Abstract translation: 一种功率肖特基整流器件，其具有填充有未掺杂多晶硅层的多个第一沟槽，并且每个第一沟槽还在所述第一沟槽的底部下方具有p区，以阻止反向电流，同时施加反向偏置; 减少少数民族承运人，同时采取正向偏见。 因此，功率肖特基整流器可以提供第一快速的开关速度。 功率肖特基整流器在衬底的外部形成有端接区域。 还提供了制造方法。