公开(公告)号：US06214745B1

公开(公告)日：2001-04-10

申请号：US09195685

申请日：1998-11-19

申请人： Ming-Sheng Yang ,  Yimin Huang ,  Juan-Yuan Wu ,  Water Lur

发明人： Ming-Sheng Yang ,  Yimin Huang ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L2131

CPC分类号： H01L21/7684 ,  H01L21/3212

摘要： A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.

摘要翻译： 化学机械抛光方法利用浅哑图形来平坦化介电层。 该方法包括以下步骤：首先在电介质层上形成浅哑图案，然后在电介质层上涂覆图案化的光致抗蚀剂层。 此后，将光致抗蚀剂层用作掩模以在电介质层的其它区域中形成开口。 随后，去除光致抗蚀剂层以露出浅哑图案，然后依次沉积胶/阻挡层和导电层。 接下来，进行化学机械抛光操作，以同时去除介电层上方的多余的导电层和胶/阻挡层以及浅哑图案。 由于介电层上方的每个区域中胶/阻挡层的去除速率大致相同，所以获得了平坦的基板表面。

公开(公告)号：US06156642A

公开(公告)日：2000-12-05

申请号：US274603

申请日：1999-03-23

申请人： Juan-Yuan Wu ,  Water Lur

发明人： Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/76834

摘要： A semiconductor fabrication method is provided for fabricating a dual damascene structure in a semiconductor device. By this method, a dielectric layer is first formed over a semiconductor substrate, and then a void structure including a via hole and a trench is formed in the dielectric layer. Next, a metallization structure is formed in the void structure in the dielectric layer, and after this, a special etching agent is used to treat the exposed surface of the metallization structure so as to make the exposed surface substantially rugged. Finally, a passivation layer is formed over the metallization structure, with the metallization structure serving as the intended dual damascene structure. The roughness of the exposed surface of the metallization structure can help buffer the stresses from the deposition of the passivation layer thereon and also help strengthen the adhesion between the passivation layer and the metallization structure, so that the passivation layer can be firmly secured to the metallization structure. As a result, the passivation layer cannot peel off the metallization structure, and thereby can more reliably help prevent the metallization structure from oxidizing and the atoms/ions in the metallization structure from diffusing into the subsequently formed dielectric layer above the metallization structure. The resultant IC device is therefore more reliable to use.

摘要翻译： 提供半导体制造方法用于在半导体器件中制造双镶嵌结构。 通过这种方法，首先在半导体衬底上形成电介质层，然后在电介质层中形成包括通孔和沟槽的空隙结构。 接下来，在电介质层的空隙结构中形成金属化结构，之后，使用特殊的蚀刻剂来处理金属化结构的露出表面，以使暴露表面基本上坚固。 最后，在金属化结构上形成钝化层，金属化结构用作预期的双镶嵌结构。 金属化结构的暴露表面的粗糙度可以帮助缓冲其上的钝化层沉积的应力，并且还有助于加强钝化层和金属化结构之间的粘附，使得钝化层可以牢固地固定到金属化 结构体。 结果，钝化层不能剥离金属化结构，从而更可靠地有助于防止金属化结构氧化，并且金属化结构中的原子/离子扩散到金属化结构之上的随后形成的电介质层。 因此，所得到的IC器件更可靠地使用。

公开(公告)号：US6097093A

公开(公告)日：2000-08-01

申请号：US165703

申请日：1998-10-02

申请人： Juan-Yuan Wu ,  Water Lur

发明人： Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L23/535

CPC分类号： H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002

摘要： A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.

摘要翻译： 双镶嵌结构包括半导体衬底，形成在衬底上的金属氧化物半导体（MOS）晶体管和金属层。 金属层通过互连电连接到MOS晶体管的导电区域。 金属层还包括第一金属间隔区域和第二金属间隔区域，其中第一金属间隔区域的宽度为器件线宽的约1至10倍，第二间隔区域的宽度为约0.8至1.2 设备线宽的倍数。 第一金属间隔区域包括用于更好的热传递速率的高介电常数电介质，并且第二间隔区域包括用于较短电阻 - 电容延迟的低介电常数介电层。

公开(公告)号：US6001694A

公开(公告)日：1999-12-14

申请号：US059752

申请日：1998-04-14

申请人： Hsueh-Hao Shih ,  Juan-Yuan Wu ,  Water Lur

发明人： Hsueh-Hao Shih ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/331 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/469 ,  H01L21/4763

CPC分类号： H01L21/28202 ,  H01L29/518

摘要： A method for adjusting the amount of doped nitride ions in a dielectric layer so that the nitride ions form bonds with silicon to increase the quality of an oxide layer. The method comprises the step of providing a silicon substrate. Next, a rapid thermal oxidation or furnace oxidation method is used to form an oxide layer over the silicon substrate. Gaseous mixtures having different ratios of nitrogen monoxide, nitrous oxide or ammonia to oxygen are concocted and then allowed to react at different reacting temperatures for controlling the nitride concentration level in the oxide layer. The nitride-doped oxide layer not only can stop the penetration of boron ions, but can also provide a stabilizing effect on the oxide layer/silicon substrate interface without degradation of electrical property, thereby improving the quality of a transistor.

摘要翻译： 一种用于调节介电层中的掺杂氮化物离子的量使得氮化物离子与硅键合以提高氧化物层的质量的方法。 该方法包括提供硅衬底的步骤。 接下来，使用快速热氧化或炉氧化方法在硅衬底上形成氧化物层。 将具有不同比例的一氧化氮，一氧化二氮或氨与氧的气态混合物混合，然后在不同的反应温度下反应，以控制氧化物层中的氮化物浓度水平。 氮化物掺杂氧化物层不仅可以阻止硼离子的渗透，而且还可以在氧化物层/硅衬底界面上提供稳定效果，而不会降低电性能，从而提高晶体管的质量。

公开(公告)号：US5959311A

公开(公告)日：1999-09-28

申请号：US172459

申请日：1998-10-14

申请人： Hsueh-Hao Shih ,  Mu-Chun Wang ,  Juan-Yuan Wu ,  Water Lur

发明人： Hsueh-Hao Shih ,  Mu-Chun Wang ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L23/485 ,  H01L23/544 ,  H01L23/58

CPC分类号： H01L24/05 ,  H01L22/34 ,  H01L23/58 ,  H01L2224/05556 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/13091 ,  H01L2924/3011

摘要： An antenna effect monitor includes a transistor formed on a semiconductor substrate. The transistor gate is coupled to a doped polysilicon interconnect layer which is also coupled to an antenna effect monitoring unit. Several metal bonding pads float in an orderly fashion above the doped polysilicon interconnect layer without coupling with each other. Several small metal layers are formed in an orderly fashion above the doped polysilicon interconnect layer but are electrically coupled together by several via plugs in between. The top small metal layer is coupled to the top bonding pad. The bottom small metal layer is electrically coupled to the doped polysilicon interconnect layer. Then a passivation layer covers the substrate but leaves a pad opening to expose the top bonding pad.

摘要翻译： 天线效应监视器包括形成在半导体衬底上的晶体管。 晶体管栅极耦合到掺杂的多晶硅互连层，其也耦合到天线效应监测单元。 几个金属接合焊盘在掺杂多晶硅互连层上方有序地浮动，而不会彼此耦合。 几个小金属层以有序的方式形成在掺杂多晶硅互连层上方，但是通过其间的几个通孔电连接在一起。 顶部小金属层耦合到顶部焊盘。 底部小金属层电耦合到掺杂多晶硅互连层。 然后钝化层覆盖衬底，但留下衬垫开口以露出顶部焊盘。

公开(公告)号：US07078346B2

公开(公告)日：2006-07-18

申请号：US10902315

申请日：2004-07-29

申请人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/311

CPC分类号： H01L21/02112 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/31612 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838

摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

公开(公告)号：US20050032328A1

公开(公告)日：2005-02-10

申请号：US10939716

申请日：2004-09-13

申请人： Ming-Sheng Yang ,  Juan-Yuan Wu ,  Water Lur

发明人： Ming-Sheng Yang ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L21/762 ,  H01L21/00 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76229

摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

摘要翻译： 公开了用于形成浅沟槽隔离的化学机械抛光的方法。 提供了具有多个有效区域的基板，包括多个相对较大的有源区域和多个相对小的有源区域。 该方法包括以下步骤。 形成衬底上的氮化硅层。 在有源区域之间形成多个浅沟槽，其中一个或多个可以构成对准标记。 在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。 在氧化物层上形成部分反向有源掩模。 部分反向有源掩模将氧化物层的一部分暴露在大的有效区域上方和对准标记之上。 去除每个大活性区域的氧化物层和对准标记。 去除部分反向主动掩模。 氧化层平坦化。

公开(公告)号：US06627387B2

公开(公告)日：2003-09-30

申请号：US09827827

申请日：2001-04-05

申请人： Kevin Hsieh ,  Chih-Yung Lin ,  Chih-Hsiang Hsiao ,  Juan-Yuan Wu ,  Water Lur

发明人： Kevin Hsieh ,  Chih-Yung Lin ,  Chih-Hsiang Hsiao ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： G03F726

CPC分类号： G03F7/091 ,  Y10S430/151

摘要： A method of photolithography. An anti-reflective coating is formed on the conductive layer. An nitrogen plasma treatment is performed. A photo-resist layer is formed and patterned on the anti-reflective coating. The conductive layer is defined. The photo-resist layer is removed. The anti-reflective layer is removed by using phosphoric acid.

公开(公告)号：US06337279B1

公开(公告)日：2002-01-08

申请号：US09215061

申请日：1998-12-17

申请人： Chao-Yuan Huang ,  Juan-Yuan Wu ,  Water Lur

发明人： Chao-Yuan Huang ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L21302

CPC分类号： H01L21/76224 ,  H01L21/31053

摘要： A method of fabricating a shallow trench isolation in semiconductor substrate comprises a densification process after performing chemical-mechanical polishing on an isolation plug. Thus, the isolation plug can prevent micro-scratches from forming deep scratches. Therefore, shorts arising from the micro-scratches do not happen.

摘要翻译： 在半导体衬底中制造浅沟槽隔离的方法包括在隔离插头上进行化学机械抛光之后的致密化过程。 因此，隔离塞可以防止微划痕形成深划痕。 因此，微刮痕产生的短路不会发生。

公开(公告)号：US06246119B1

公开(公告)日：2001-06-12

申请号：US09432884

申请日：1999-11-02

申请人： Juan-Yuan Wu ,  Water Lur

发明人： Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L23535

CPC分类号： H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.

摘要翻译： 双镶嵌结构包括半导体衬底，形成在衬底上的金属氧化物半导体（MOS）晶体管和金属层。 金属层通过互连电连接到MOS晶体管的导电区域。 金属层还包括第一金属间隔区域和第二金属间隔区域，其中第一金属间隔区域的宽度为器件线宽的约1至10倍，第二间隔区域的宽度为约0.8至1.2 设备线宽的倍数。 第一金属间隔区域包括用于更好的热传递速率的高介电常数电介质，并且第二间隔区域包括用于较短电阻 - 电容延迟的低介电常数介电层。