公开(公告)号：US20110233522A1

公开(公告)日：2011-09-29

申请号：US12731241

申请日：2010-03-25

申请人： Guy Cohen ,  Conal E. Murray ,  Michael J. Rooks

发明人： Guy Cohen ,  Conal E. Murray ,  Michael J. Rooks

IPC分类号： H01L29/267 ,  H01L21/84

CPC分类号： H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

摘要： Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

摘要翻译： 提供了在纳米级基于沟道的场效应晶体管（FET）中嵌入硅锗（e-SiGe）源极和漏极应力的技术。 一方面，制造FET的方法包括以下步骤。 提供其上具有电介质的掺杂衬底。 在电介质上放置至少一个硅（Si）纳米线。 掩模纳米线的一个或多个部分，使纳米线的其它部分暴露出来。 外延锗（Ge）生长在纳米线的暴露部分上。 外延Ge与纳米线中的Si相互扩散以形成纳米线中嵌入纳米线中的压应变的SiGe区域。 掺杂衬底用作FET的栅极，纳米线的掩蔽掉的部分用作FET的沟道，并且嵌入的SiGe区域用作FET的源极和漏极区域。

公开(公告)号：US07811906B1

公开(公告)日：2010-10-12

申请号：US12612331

申请日：2009-11-04

申请人： Ageeth A. Bol ,  Jack O. Chu ,  Alfred Grill ,  Conal E. Murray ,  Katherine L. Saenger

发明人： Ageeth A. Bol ,  Jack O. Chu ,  Alfred Grill ,  Conal E. Murray ,  Katherine L. Saenger

IPC分类号： H01L21/36 ,  H01L21/20 ,  H01L21/44 ,  H01L21/31

CPC分类号： H01L21/32139 ,  H01L21/762

摘要： An in-place bonding method in which a metal template layer under a carbon layer is removed while the carbon layer is still attached to a substrate is described for forming a carbon-on-insulator substrate. In one embodiment of the in-place bonding method, at least one layered metal/carbon (M/C) region is formed on an insulating surface layer of an initial substrate structure. The at least one layered M/C region has edges that are bordered by exposed regions of the insulating surface layer. Some edges of the at least one layered M/C region are then secured to a base substrate of the initial structure via a securing structure, while other edges are left exposed. A selective metal etchant removes the metal layer under the carbon layer using the exposed edges for access. After metal etching, the now-unsupported carbon layer bonds to the underlying insulating surface layer by attraction.

摘要翻译： 为了形成绝缘体上的基板，描述了其中在碳层仍然附着到基板上时除去碳层下面的金属模板层的就地结合方法。 在就地接合方法的一个实施例中，在初始衬底结构的绝缘表面层上形成至少一个层状金属/碳（M / C）区域。 所述至少一层分层的M / C区域具有与绝缘表面层的暴露区域相邻的边缘。 然后，至少一层分层M / C区域的一些边缘经由固定结构固定到初始结构的基底，同时其它边缘被暴露。 选择性金属蚀刻剂使用暴露的边缘去除碳层下方的金属层以进入。 在金属蚀刻之后，现在无载体的碳层通过吸引而结合到下面的绝缘表面层。

公开(公告)号：US09058887B2

公开(公告)日：2015-06-16

申请号：US11928258

申请日：2007-10-30

申请人： Louis C. Hsu ,  Conal E. Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Conal E. Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

IPC分类号： G06F17/50 ,  G11C17/18 ,  H04L12/701 ,  H04L29/08

CPC分类号： G11C17/18 ,  G06F17/5045 ,  H04L29/08072 ,  H04L45/00

摘要： The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

摘要翻译： 本发明提供了一种可再编程的电可熔熔丝和相关的设计结构。 电可熔熔丝使用电迁移效应进行编程，并使用反向电迁移效应重新编程。 可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。

公开(公告)号：US08802563B2

公开(公告)日：2014-08-12

申请号：US13603051

申请日：2012-09-04

申请人： Chih-Chao Yang ,  Conal E. Murray

发明人： Chih-Chao Yang ,  Conal E. Murray

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  Y02P80/30 ,  H01L2924/00

摘要： A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material.

摘要翻译： 提供了一种方法，其包括提供具有约4.0或更小的介电常数的介电材料和嵌入其中的至少一种导电材料，所述至少一种导电材料具有与电介质材料的上表面共面的上表面， 所述至少一个导电材料的上表面具有向内延伸到所述至少一个导电材料中的中空金属相关缺陷; 并用表面修复材料填充与中空金属相关的缺陷。

公开(公告)号：US08624395B2

公开(公告)日：2014-01-07

申请号：US13400900

申请日：2012-02-21

申请人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L23/48

CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.

摘要翻译： 提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连以及IC互连的制造方法。 一种结构包括层间电线之间的交叉处的通孔簇结构。 通孔结构包括多个通孔，每个通孔填充有金属并衬有衬垫材料。 至少两个相邻的通孔彼此接触并且多个通孔降低了层间电线之间的电流负载。

公开(公告)号：US08564025B2

公开(公告)日：2013-10-22

申请号：US13566594

申请日：2012-08-03

申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Conal E. Murray ,  Jeffrey W. Sleight

发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Conal E. Murray ,  Jeffrey W. Sleight

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/42392 ,  H01L29/7845 ,  H01L29/78696

摘要： An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.

摘要翻译： 提供了一种中间处理装置，包括连接第一和第二绝缘体上硅（SOI）焊盘的纳米线，包括围绕该纳米线的栅极导体和围绕该栅极导体的多晶硅的栅极以及设置成与该栅极导体反应的硅化物形成金属 多晶硅以形成完全硅化（FUSI）材料以在纳米线中诱导径向应变。

公开(公告)号：US08445892B2

公开(公告)日：2013-05-21

申请号：US13554065

申请日：2012-07-20

申请人： Guy Cohen ,  Conal E. Murray ,  Michael J. Rooks

发明人： Guy Cohen ,  Conal E. Murray ,  Michael J. Rooks

IPC分类号： H01L29/775

CPC分类号： H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

摘要： Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

公开(公告)号：US20120329270A1

公开(公告)日：2012-12-27

申请号：US13603051

申请日：2012-09-04

申请人： Chih-Chao Yang ,  Conal E. Murray

发明人： Chih-Chao Yang ,  Conal E. Murray

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  Y02P80/30 ,  H01L2924/00

摘要： A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material.

摘要翻译： 提供了一种方法，其包括提供具有约4.0或更小的介电常数的介电材料和嵌入其中的至少一种导电材料，所述至少一种导电材料具有与电介质材料的上表面共面的上表面， 所述至少一个导电材料的上表面具有向内延伸到所述至少一个导电材料中的中空金属相关缺陷; 并用表面修复材料填充与中空金属相关的缺陷。

公开(公告)号：US20120286377A1

公开(公告)日：2012-11-15

申请号：US13103193

申请日：2011-05-09

申请人： Josephine B. Chang ,  Sebastian U. Engelmann ,  Michael A. Guillorn ,  Fei Liu ,  Conal E. Murray

发明人： Josephine B. Chang ,  Sebastian U. Engelmann ,  Michael A. Guillorn ,  Fei Liu ,  Conal E. Murray

IPC分类号： H01L29/84 ,  H01L21/3105 ,  H01L29/06

CPC分类号： H01L29/84 ,  B81B3/0072 ,  B81B2203/0109 ,  B81B2203/0307 ,  H01L29/0673

摘要： Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions.

摘要翻译： 改进的纳米机电系统设备及其制造的结构及系统和技术。 在一个实施例中，结构包括分别通过第一和第二绝缘支撑点从第一和第二锚定点分离的下面的基底。 第一和第二锚定点通过梁连接。 第一和第二沉积区域分别覆盖在第一和第二锚定点上，并且第一和第二沉积区域分别在第一和第二锚定点上施加压缩。 第一和第二锚固点上的压缩在梁上产生相反的力，使梁受到拉伸应力。 第一和第二沉积区域适当地呈现具有随其厚度变化的可实现最大值的内部拉伸应力，使得施加在梁上的拉伸应力至少部分地取决于第一和第二沉积区域的厚度。

公开(公告)号：US08138603B2

公开(公告)日：2012-03-20

申请号：US12115817

申请日：2008-05-06

申请人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid out in parallel and each of which are coated with a liner material. Two adjacent of the wires are physically contacted to each other.

摘要翻译： 提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连，提供IC互连的设计结构和IC互连的制造方法。 该结构具有电迁移免疫性和设计冗余性，其包括并列布置的多根线，并且每条线都涂有衬里材料。 电线的两个相互物理接触。