公开(公告)号：US08962410B2

公开(公告)日：2015-02-24

申请号：US13282210

申请日：2011-10-26

申请人： Da Zhang ,  Konstantin V. Loiko ,  Spencer E. Williams ,  Brian A. Winstead

发明人： Da Zhang ,  Konstantin V. Loiko ,  Spencer E. Williams ,  Brian A. Winstead

IPC分类号： H01L21/337 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823493 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823892

摘要： A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.

摘要翻译： 第一晶体管和第二晶体管形成有不同的阈值电压。 第一栅极形成在用于第一晶体管的衬底的第一区域上，并且在第二区域上形成用于第二晶体管的第二栅极。 第一个区域被屏蔽。 通过在掩蔽第一区域的同时通过第二栅极注入来调节第二晶体管的阈值电压。 电流电极区域形成在第二栅极的相对侧上的第一栅极和电流电极区域的相对侧上。

公开(公告)号：US20130102143A1

公开(公告)日：2013-04-25

申请号：US13279807

申请日：2011-10-24

申请人： Da Zhang ,  Frank K. Baker, JR.

发明人： Da Zhang ,  Frank K. Baker, JR.

IPC分类号： H01L21/28

CPC分类号： H01L21/32139 ,  H01L27/11521 ,  H01L29/40114

摘要： Forming an NVM structure includes forming a floating gate layer; forming a first dielectric layer over the floating gate layer; forming a plurality of nanocrystals over the first dielectric layer; etching the first dielectric layer using the plurality of nanocrystals as a mask to form dielectric structures, wherein the floating gate layer is exposed between adjacent dielectric structures; etching a first depth into the floating gate layer using the plurality of dielectric structures as a mask to form a plurality of patterned structures, wherein the first depth is less than a thickness of the floating gate layer; patterning the floating gate layer to form a floating gate; forming a second dielectric layer over the floating gate, wherein the second dielectric layer is formed over the patterned structures and on the floating gate layer between adjacent patterned structures; and forming a control gate layer over the second dielectric layer.

摘要翻译： 形成NVM结构包括形成浮栅层; 在所述浮栅上形成第一电介质层; 在所述第一介电层上形成多个纳米晶体; 使用所述多个纳米晶体作为掩模蚀刻所述第一介电层以形成电介质结构，其中所述浮栅层暴露在相邻的介质结构之间; 使用所述多个介电结构作为掩模将第一深度蚀刻到所述浮栅中，以形成多个图案化结构，其中所述第一深度小于所述浮栅层的厚度; 图案化浮栅层以形成浮栅; 在所述浮置栅极上形成第二电介质层，其中所述第二介电层形成在所述图案化结构之上，并且在相邻图案化结构之间的所述浮栅层上形成; 以及在所述第二电介质层上形成控制栅极层。

公开(公告)号：US08299545B2

公开(公告)日：2012-10-30

申请号：US12695565

申请日：2010-01-28

申请人： Xiangdong Chen ,  Geng Wang ,  Da Zhang

发明人： Xiangdong Chen ,  Geng Wang ,  Da Zhang

IPC分类号： H01L29/02

CPC分类号： H01L29/1083 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78

摘要： A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.

摘要翻译： 一种方法和结构在衬底内注入第一种杂质以在衬底内邻近衬底的顶表面形成沟道区; 在通道区域上方的衬底的顶表面上形成栅极堆叠; 并且在所述衬底内注入第二类型杂质以在所述衬底内邻近所述顶表面形成源区和漏区。 沟道区域位于源区和漏区之间。 第二种杂质相对于第一种杂质具有相反的极性。 所述方法和结构相对于沟道区域内的第一类型杂质的浓度注入更大浓度的第一类型杂质，以在衬底下方（相对于顶表面）在通道内形成主体掺杂区域 地区; 并且在源极和漏极区域之下（相对于顶表面）下方的衬底内形成辅助体掺杂区域。

公开(公告)号：US08104954B2

公开(公告)日：2012-01-31

申请号：US12309183

申请日：2007-10-24

申请人： Zhi Xie ,  Zhenwei Hu ,  Ying Ci ,  Da Zhang

发明人： Zhi Xie ,  Zhenwei Hu ,  Ying Ci ,  Da Zhang

IPC分类号： B22D11/16 ,  G01J5/08

CPC分类号： G01J5/04 ,  B22D2/00 ,  G01J5/0022 ,  G01J5/004 ,  G01J5/047 ,  G01J5/08 ,  G01J5/0846 ,  G01J2005/0077 ,  G01J2005/068

摘要： The present invention discloses a method and apparatus for measuring the temperature field on the surface of casting billet/slab, including: a thermal imager, an infrared radiation thermometer, a mechanical scanning unit, an image and data processing system; the thermal imager, the infrared radiation thermometer and the mechanical scanning unit are respectively connected to the image and data processing system; the infrared radiation thermometer is installed on the mechanical scanning unit and can measure the temperature of casting billet/slab surface by scanning; the thermal imager can measure the temperature of a certain area on the surface of casting billet/slab by thermal imaging. The present invention makes use of the combination of high-resolution thermal imager and scan-type infrared radiation thermometer, through the model-based filtering method, overcomes the influence of iron scales on the surface of casting billet/slab, and implements real-time stable measurement of surface temperature of casting billet/slab.

摘要翻译： 本发明公开了一种测量铸坯/板坯表面温度场的方法和装置，包括：热像仪，红外辐射温度计，机械扫描单元，图像和数据处理系统; 热像仪，红外辐射温度计和机械扫描单元分别连接到图像和数据处理系统; 红外辐射温度计安装在机械扫描装置上，可以通过扫描测量铸坯/板坯表面的温度; 热成像仪可以通过热成像测量铸坯/板坯表面某一面积的温度。 本发明利用高分辨率热成像仪和扫描型红外辐射温度计的组合，通过基于模型的滤波方法，克服了铁鳞对铸坯/板坯表面的影响，实现了实时 稳定的铸坯/板坯表面温度测量。

公开(公告)号：US08039341B2

公开(公告)日：2011-10-18

申请号：US11428953

申请日：2006-07-06

申请人： Voon-Yew Thean ,  Bich-Yen Nguyen ,  Da Zhang

发明人： Voon-Yew Thean ,  Bich-Yen Nguyen ,  Da Zhang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2 or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.

摘要翻译： 半导体制造工艺包括掩蔽半导体晶片的第一区域（例如，NMOS区域），例如双轴拉伸应变绝缘体上硅（SOI）晶片，并在第二晶片区域的源极/漏极区域中产生凹陷，例如 ，PMOS区域。 然后将晶片在促进硅迁移的环境中退火。 源极/漏极凹槽用源极/漏极结构填充，例如通过外延生长。 退火环境可以包括保持在约800至1000℃范围内的温度的氢气种类，例如H 2或GeH 2。第二区域可以是硅，并且源极/漏极结构可以是硅锗。 创建凹槽可以包括用第一蚀刻工艺创建浅凹槽，执行非晶化注入以产生非晶层，执行惰性环境退火以使非晶层重结晶，以及用第二蚀刻工艺加深浅凹槽。

公开(公告)号：US20110063628A1

公开(公告)日：2011-03-17

申请号：US12994410

申请日：2008-10-28

申请人： Zhi Xie ,  Zhenwei Hu ,  Ying Ci ,  Da Zhang

发明人： Zhi Xie ,  Zhenwei Hu ,  Ying Ci ,  Da Zhang

IPC分类号： G01B11/14 ,  G01F23/00

CPC分类号： G01F23/22 ,  B22D2/003 ,  G01F23/0076 ,  G01F23/04 ,  G01F23/292

摘要： An apparatus for measuring the liquid level of molten metal comprises an image measuring device (5), a measuring probe (6), a lifting mechanism (1), a displacement sensor (11), an data processing system (4) and a correction marker(7). The lifting mechanism (1) is fixed to the molten metal container (10) or is independent of the molten metal container, the image measuring device (5) and the measuring probe (6) are installed on the lifting mechanism (1) or are independent of the lifting mechanism, and the optical axis of the image measuring device (5) is set at an angle with the geometric axis of the measuring probe (6), the measuring probe (6) is located within the field of view of the image measuring device (5), the image measuring device (5), the lifting mechanism (1) and the displacement sensor (11) are connected to the data processing system (4) respectively. A method for measuring the level of molten metal is also disclosed. The present invention is able to eliminate the influence by the slag layer floating on the molten metal and to achieve stably and continuously accurate measurement of molten metal level by using the measuring probe (6) inserting into molten metal through the slag-metal interface and having the slag thickness information after lifted.

摘要翻译： 一种测量熔融金属液位的装置，包括图像测量装置（5），测量探针（6），提升机构（1），位移传感器（11），数据处理系统（4）和校正 标记（7）。 提升机构（1）固定在熔融金属容器（10）上，或与熔融金属容器无关，图像测量装置（5）和测量探头（6）安装在提升机构（1）上，或者 独立于提升机构，并且图像测量装置（5）的光轴与测量探针（6）的几何轴线成一定角度，测量探头（6）位于 图像测量装置（5），图像测量装置（5），提升机构（1）和位移传感器（11）分别连接到数据处理系统（4）。 还公开了一种用于测量熔融金属的水平的方法。 本发明能够消除漂浮在熔融金属上的熔渣层的影响，并且通过使用测量探头（6）通过熔渣金属界面将其插入到熔融金属中并且具有 炉渣厚度信息提升后。

公开(公告)号：US20100236743A1

公开(公告)日：2010-09-23

申请号：US12309183

申请日：2007-10-24

申请人： Zhi Xie ,  Zhenwei Hu ,  Ying Ci ,  Da Zhang

发明人： Zhi Xie ,  Zhenwei Hu ,  Ying Ci ,  Da Zhang

IPC分类号： B22D46/00 ,  B22C19/00 ,  B22D2/00

CPC分类号： G01J5/04 ,  B22D2/00 ,  G01J5/0022 ,  G01J5/004 ,  G01J5/047 ,  G01J5/08 ,  G01J5/0846 ,  G01J2005/0077 ,  G01J2005/068

摘要： The present invention discloses a method and apparatus for measuring the temperature field on the surface of casting billet/slab, including: a thermal imager, an infrared radiation thermometer, a mechanical scanning unit, an image and data processing system; the thermal imager, the infrared radiation thermometer and the mechanical scanning unit are respectively connected to the image and data processing system; the infrared radiation thermometer is installed on the mechanical scanning unit and can measure the temperature of casting billet/slab surface by scanning; the thermal imager can measure the temperature of a certain area on the surface of casting billet/slab by thermal imaging. The present invention makes use of the combination of high-resolution thermal imager and scan-type infrared radiation thermometer, through the model-based filtering method, overcomes the influence of iron scales on the surface of casting billet/slab, and implements real-time stable measurement of surface temperature of casting billet/slab.

摘要翻译： 本发明公开了一种测量铸坯/板坯表面温度场的方法和装置，包括：热像仪，红外辐射温度计，机械扫描单元，图像和数据处理系统; 热像仪，红外辐射温度计和机械扫描单元分别连接到图像和数据处理系统; 红外辐射温度计安装在机械扫描装置上，可以通过扫描测量铸坯/板坯表面的温度; 热成像仪可以通过热成像测量铸坯/板坯表面某一面积的温度。 本发明利用高分辨率热成像仪和扫描型红外辐射温度计的组合，通过基于模型的滤波方法，克服了铁鳞对铸坯/板坯表面的影响，实现了实时 稳定的铸坯/板坯表面温度测量。

公开(公告)号：US07727870B2

公开(公告)日：2010-06-01

申请号：US11737496

申请日：2007-04-19

申请人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

发明人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

IPC分类号： H01L21/3205

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

摘要翻译： 一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。 该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。 该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。 该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。

公开(公告)号：US07687337B2

公开(公告)日：2010-03-30

申请号：US11779318

申请日：2007-07-18

申请人： Da Zhang ,  Mark C. Foisy

发明人： Da Zhang ,  Mark C. Foisy

IPC分类号： H01L21/336

CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A transistor is formed by providing a semiconductor layer and forming a control electrode overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode. A first stressor is formed within the first recess and has a first doping profile. A second stressor is formed within the second recess and has the first doping profile. A third stressor is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.

摘要翻译： 通过提供半导体层并形成覆盖半导体层的控制电极来形成晶体管。 半导体层的一部分被去除控制电极的横向，以在控制电极的相对侧上形成第一凹部和第二凹部。 第一应力器形成在第一凹槽内并具有第一掺杂分布。 第二应力器形成在第二凹槽内并具有第一掺杂分布。 形成第三应激源，覆盖第一应激源。 第三应力源具有比第一轮廓具有更高的电极电流掺杂浓度的第二掺杂分布。 覆盖第二应激源的第四应力器形成并具有第二掺杂分布。 晶体管的第一电流电极和第二电流电极分别包括第三应力源和第四应力源的至少一部分。

公开(公告)号：US20100019328A1

公开(公告)日：2010-01-28

申请号：US12177986

申请日：2008-07-23

申请人： Da Zhang ,  Chendong Zhu ,  Xiangdong Chen ,  Melanie Sherony

发明人： Da Zhang ,  Chendong Zhu ,  Xiangdong Chen ,  Melanie Sherony

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0629 ,  H01L28/20

摘要： A semiconductor process and apparatus fabricate a metal gate electrode (30) and an integrated semiconductor resistor (32) by forming a metal-based layer (26) and semiconductor layer (28) over a gate dielectric layer (24) and then selectively implanting the resistor semiconductor layer (28) in a resistor area (97) to create a conductive upper region (46) and a conduction barrier (47), thereby confining current flow in the resistor semiconductor layer (36) to only the top region (46) in the finally formed device.

摘要翻译： 一种半导体工艺和装置，通过在栅极介电层（24）上形成金属基层（26）和半导体层（28），然后选择性地植入金属栅电极（30）和集成半导体电阻器（32） 电阻器区域（97）中的电阻器半导体层（28），以产生导电上部区域（46）和导电屏障（47），从而将电流流入电阻器半导体层（36）中仅限于顶部区域（46） 在最终形成的装置。