公开(公告)号：US20080261362A1

公开(公告)日：2008-10-23

申请号：US11737496

申请日：2007-04-19

申请人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

发明人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

摘要翻译： 一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。 该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。 该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。 该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。

公开(公告)号：US07727870B2

公开(公告)日：2010-06-01

申请号：US11737496

申请日：2007-04-19

申请人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

发明人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

IPC分类号： H01L21/3205

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

摘要翻译： 一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。 该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。 该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。 该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。

公开(公告)号：US07678698B2

公开(公告)日：2010-03-16

申请号：US11744581

申请日：2007-05-04

申请人： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

发明人： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

IPC分类号： H01L21/44

CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3185 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

摘要翻译： 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二张应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。

公开(公告)号：US07799650B2

公开(公告)日：2010-09-21

申请号：US11835547

申请日：2007-08-08

申请人： Xiangzheng Bo ,  Venkat R. Kolagunta ,  Konstantin V. Loiko

发明人： Xiangzheng Bo ,  Venkat R. Kolagunta ,  Konstantin V. Loiko

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.

摘要翻译： 在半导体材料层上形成半导体器件的方法包括在半导体材料层上形成栅极结构。 该方法还包括形成邻近栅极结构的第一氮化物间隔区，并在半导体材料层中形成源极/漏极延伸部分。 该方法还包括形成覆盖栅极结构和源极/漏极延伸部的氧化物衬垫。 该方法还包括在氧化物衬垫附近形成第二氮化物间隔物。 该方法还包括在半导体材料层中形成源/漏区。 该方法还包括使用对氧化物衬垫有选择性的蚀刻工艺，去除第二氮化物间隔物。 该方法还包括使用对第一氮化物间隔物具有选择性的蚀刻工艺，至少部分地去除氧化物衬垫。 该方法还包括形成覆盖源极/漏极区域和栅极结构的硅化物区域。

公开(公告)号：US20090042351A1

公开(公告)日：2009-02-12

申请号：US11835547

申请日：2007-08-08

申请人： Xiangzheng Bo ,  Venkat R. Kolagunta ,  Konstantin V. Loiko

发明人： Xiangzheng Bo ,  Venkat R. Kolagunta ,  Konstantin V. Loiko

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.

摘要翻译： 在半导体材料层上形成半导体器件的方法包括在半导体材料层上形成栅极结构。 该方法还包括形成邻近栅极结构的第一氮化物间隔区，并在半导体材料层中形成源极/漏极延伸部分。 该方法还包括形成覆盖栅极结构和源极/漏极延伸部的氧化物衬垫。 该方法还包括在氧化物衬垫附近形成第二氮化物间隔物。 该方法还包括在半导体材料层中形成源极/漏极区域。 该方法还包括使用对氧化物衬垫有选择性的蚀刻工艺，去除第二氮化物间隔物。 该方法还包括使用对第一氮化物间隔物具有选择性的蚀刻工艺，至少部分地去除氧化物衬垫。 该方法还包括形成覆盖源极/漏极区域和栅极结构的硅化物区域。

公开(公告)号：US20080272411A1

公开(公告)日：2008-11-06

申请号：US11744581

申请日：2007-05-04

申请人： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

发明人： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3185 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

摘要翻译： 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二拉伸应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。

公开(公告)号：US07514313B2

公开(公告)日：2009-04-07

申请号：US11400945

申请日：2006-04-10

申请人： Omar Zia ,  Da Zhang ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Bich-Yen Nguyen

发明人： Omar Zia ,  Da Zhang ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Bich-Yen Nguyen

IPC分类号： H01L21/98 ,  H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

摘要翻译： 形成电子器件的工艺可以包括在第一和第二有源区上形成绝缘层和场隔离区。 该方法还可以包括形成种子层并暴露第一有源区。 该方法还可以包括分别在第一有源区和种子层上选择性地形成第一和第二半导体层。 第一和第二半导体层可以彼此间隔开。 在一个方面，该方法可以包括在基本相同的时间点同时选择性地形成第一和第二半导体层。 在另一方面，电子设备可以包括由场隔离区分隔开并由导电构件电连接的第一和第二晶体管结构。 设计为电浮置的半导体岛可以位于导电构件和基底层之间。

公开(公告)号：US07067868B2

公开(公告)日：2006-06-27

申请号：US10952676

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

IPC分类号： H01L27/108

CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78687

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

公开(公告)号：US07018901B1

公开(公告)日：2006-03-28

申请号：US10954121

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

IPC分类号： H01L21/336

CPC分类号： H01L21/2254 ,  H01L29/665 ,  H01L29/66787 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78648

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

摘要翻译： 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

公开(公告)号：US20120302022A1

公开(公告)日：2012-11-29

申请号：US13117191

申请日：2011-05-27

申请人： Venkat R. Kolagunta

发明人： Venkat R. Kolagunta

IPC分类号： H01L21/8234

CPC分类号： H01L21/823857 ,  H01L21/82385

摘要： A method for fabricating at least three different types of devices on a semiconductor substrate comprises forming a first electrode region and a second electrode region for a first semiconductor device at the same time as forming a first electrode region of a asymmetrical semiconductor device, and forming a first electrode region and a second electrode region for a second semiconductor device at the same time as forming a second electrode region of the asymmetrical semiconductor device.

摘要翻译： 一种用于在半导体衬底上制造至少三种不同类型的器件的方法包括在形成第一半导体器件的第一电极区域和第二电极区域的同时形成非对称半导体器件的第一电极区域，并形成 第一电极区域和用于第二半导体器件的第二电极区域，同时形成非对称半导体器件的第二电极区域。