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    System and method correcting optical proximity effect using pattern configuration dependent OPC models
    31.
    发明授权
    System and method correcting optical proximity effect using pattern configuration dependent OPC models 有权
    使用模式配置依赖OPC模型的系统和方法校正光学邻近效应

    公开(公告)号：US07900170B2

    公开(公告)日：2011-03-01

    申请号：US11585086

    申请日：2006-10-24

    申请人： Sung-Soo Suh ,  Young-Seog Kang ,  Han-Ku Cho ,  Sang-Gyun Woo

    发明人： Sung-Soo Suh ,  Young-Seog Kang ,  Han-Ku Cho ,  Sang-Gyun Woo

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics and a mask layout generation unit including a model selector selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the plurality of OPC models and the generated IC layout, the mask layout generation unit generating a mask layout based on the IC layout and the selected second plurality of OPC models. A first example method may include storing a first plurality OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics, generating an IC layout, selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the first plurality of OPC models and the generated IC layout and generating a mask layout based on the generated IC layout and the selected second plurality of OPC models. A second example method may include applying a first OPC model to a first portion of a generated integrated circuit (IC) layout, applying a second OPC model to a second portion of the generated IC layout and generating a mask layout based on the generated IC layout after the application of the first and second OPC models.

    摘要翻译： 提供光学邻近校正（OPC）系统及其方法。 示例性OPC系统可以包括产生IC布局的集成电路（IC）布局生成单元，存储第一多个OPC模型的数据库单元，与多个目标特定特征之一相关联的第一多个OPC模型中的每一个，以及 掩模布局生成单元，其包括基于与所述多个OPC模型相关联的目标特定特性与所生成的IC布局之间的比较来选择第二多个OPC模型的模型选择器，所述掩模布局生成单元基于所述多个OPC模型生成掩模布局 IC布局和所选择的第二批OPC模型。 第一示例性方法可以包括存储第一多个OPC模型，所述第一多个OPC模型中的每一个与多个目标特定特征中的一个相关联，生成IC布局，基于所述多个OPC模型之间的比较来选择第二多个OPC模型 与第一多个OPC模型相关联的目标特定特征和所生成的IC布局，并且基于所生成的IC布局和所选择的第二多个OPC模型生成掩模布局。 第二示例性方法可以包括将第一OPC模型应用于所生成的集成电路（IC）布局的第一部分，将第二OPC模型应用于所生成的IC布局的第二部分，并且基于所生成的IC布局生成掩模布局 之后应用了第一个和第二个OPC模型。

    OPTICAL MASKS AND METHODS FOR MEASURING ABERRATION OF A BEAM
    32.
    发明申请
    OPTICAL MASKS AND METHODS FOR MEASURING ABERRATION OF A BEAM 失效
    用于测量光束的光学掩模和方法

    公开(公告)号：US20100112466A1

    公开(公告)日：2010-05-06

    申请号：US12686093

    申请日：2010-01-12

    申请人： Chan Hwang ,  Suk-Joo Lee ,  Han-Ku Cho ,  Sang-Gyun Woo

    发明人： Chan Hwang ,  Suk-Joo Lee ,  Han-Ku Cho ,  Sang-Gyun Woo

    IPC分类号： G03F1/00

    CPC分类号： G03F7/706 ,  G03F1/44

    摘要： An optical mask for use with an exposure beam includes a mask substrate adapted to be placed on a traveling path of the exposure beam. A reference pattern is formed on the mask substrate. The reference pattern is adapted to direct the exposure beam to travel in a predetermined reference direction. A comparative pattern is formed on the mask substrate. The comparative pattern is adapted to direct the exposure beam to travel in a direction inclined at a predetermined angle with respect to the reference direction.

    摘要翻译： 用于曝光光束的光学掩模包括适于放置在曝光光束的行进路径上的掩模基板。 在掩模基板上形成参考图案。 参考图案适于引导曝光光束在预定的参考方向上行进。 在掩模基板上形成比较图案。 比较图案适于引导曝光光束相对于参考方向在以预定角度倾斜的方向上行进。

    Optical masks and methods for measuring aberration of a beam
    33.
    发明授权
    Optical masks and methods for measuring aberration of a beam 有权
    用于测量光束像差的光学掩模和方法

    公开(公告)号：US07670725B2

    公开(公告)日：2010-03-02

    申请号：US11311109

    申请日：2005-12-19

    申请人： Chan Hwang ,  Suk-Joo Lee ,  Han-Ku Cho ,  Sang-Gyun Woo

    发明人： Chan Hwang ,  Suk-Joo Lee ,  Han-Ku Cho ,  Sang-Gyun Woo

    IPC分类号： G03F1/00

    CPC分类号： G03F7/706 ,  G03F1/44

    摘要： An optical mask for use with an exposure beam includes a mask substrate adapted to be placed on a traveling path of the exposure beam. A reference pattern is formed on the mask substrate. The reference pattern is adapted to direct the exposure beam to travel in a predetermined reference direction. A comparative pattern is formed on the mask substrate. The comparative pattern is adapted to direct the exposure beam to travel in a direction inclined at a predetermined angle with respect to the reference direction.

    摘要翻译： 用于曝光光束的光学掩模包括适于放置在曝光光束的行进路径上的掩模基板。 在掩模基板上形成参考图案。 参考图案适于引导曝光光束在预定的参考方向上行进。 在掩模基板上形成比较图案。 比较图案适于引导曝光光束相对于参考方向在以预定角度倾斜的方向上行进。

    Nonvolatile memory device and method of manufacturing the same
    34.
    发明授权
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07678650B2

    公开(公告)日：2010-03-16

    申请号：US12453721

    申请日：2009-05-20

    申请人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

    发明人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

    IPC分类号： H01L21/8247

    CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521

    摘要： Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

    摘要翻译： 示例性实施例提供了一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。

    Nonvolatile memory device and method of manufacturing the same
    35.
    发明申请
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20090258473A1

    公开(公告)日：2009-10-15

    申请号：US12453721

    申请日：2009-05-20

    申请人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

    发明人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

    IPC分类号： H01L21/762

    CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521

    摘要： Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

    摘要翻译： 示例性实施例提供了一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。

    Mask pattern for semiconductor device fabrication, method of forming the same, and method of fabricating finely patterned semiconductor device
    38.
    发明申请
    Mask pattern for semiconductor device fabrication, method of forming the same, and method of fabricating finely patterned semiconductor device 失效
    用于半导体器件制造的掩模图案，其形成方法以及制造精细图案化的半导体器件的方法

    公开(公告)号：US20060046205A1

    公开(公告)日：2006-03-02

    申请号：US11186913

    申请日：2005-07-21

    申请人： Jung-Hwan Hah ,  Jin Hong ,  Hyun-Woo Kim ,  Hata Mitsuhiro ,  Kolake Subramanya ,  Sang-Gyun Woo

    发明人： Jung-Hwan Hah ,  Jin Hong ,  Hyun-Woo Kim ,  Hata Mitsuhiro ,  Kolake Subramanya ,  Sang-Gyun Woo

    IPC分类号： G03F7/00

    CPC分类号： G03F7/40 ,  B82Y30/00 ,  G03F7/0752 ,  G03F7/165 ,  H01L21/0274

    摘要： Provided are a mask pattern including a silicon-containing self-assembled molecular layer, a method of forming the same, and a method of fabricating a semiconductor device. The mask pattern includes a resist pattern formed on a semiconductor substrate and the self-assembled molecular layer formed on the resist pattern. The self-assembled molecular layer has a silica network formed by a sol-gel reaction. To form the mask pattern, first, the resist pattern is formed with openings on an underlayer covering the substrate to expose the underlayer to a first width. Then, the self-assembled molecular layer is selectively formed only on a surface of the resist pattern to expose the underlayer to a second width smaller than the first width. The underlayer is etched by using the resist pattern and the self-assembled molecular layer as an etching mask to obtain a fine pattern.

    摘要翻译： 提供了包括含硅自组装分子层的掩模图案，其形成方法和制造半导体器件的方法。 掩模图案包括形成在半导体衬底上的抗蚀剂图案和形成在抗蚀剂图案上的自组装分子层。 自组装分子层具有通过溶胶 - 凝胶反应形成的二氧化硅网络。 为了形成掩模图案，首先，在覆盖基板的下层上形成抗蚀剂图案，使底层暴露于第一宽度。 然后，仅在抗蚀剂图案的表面上选择性地形成自组装分子层，以使底层暴露于小于第一宽度的第二宽度。 通过使用抗蚀剂图案和自组装分子层作为蚀刻掩模来蚀刻底层以获得精细图案。