公开(公告)号：US07043656B2

公开(公告)日：2006-05-09

申请号：US10352711

申请日：2003-01-28

申请人： Dwight D. Riley

发明人： Dwight D. Riley

IPC分类号： G06F1/04

CPC分类号： G06F13/4022

摘要： Interconnect logic performs a transaction on an interconnect. The transaction may include multiple phases and the interconnect logic may include a counter state machine coupled to an interconnect state machine. The counter state machine may assert a signal to the interconnect state machine that may cause the interconnect state machine to prolong one or more phases of the transaction.

摘要翻译： 互连逻辑在互连上执行事务。 事务可以包括多个阶段，并且互连逻辑可以包括耦合到互连状态机的计数器状态机。 计数器状态机可以向互连状态机施加信号，这可能导致互连状态机延长交易的一个或多个阶段。

公开(公告)号：US06915446B2

公开(公告)日：2005-07-05

申请号：US09967612

申请日：2001-09-29

申请人： Dwight D. Riley

发明人： Dwight D. Riley

IPC分类号： G06F11/00 ,  G06F11/08 ,  G06F11/10

CPC分类号： G06F11/10 ,  H04L1/0041 ,  H04L1/0071 ,  H04L1/0079 ,  H04L2001/0094

摘要： An error correction code mechanism for the extensions to the peripheral component interconnect bus system (PCI-X) used in computer systems is fully backward compatible with the full PCI protocol. The error correction code check-bits can be inserted to provide error correction capability for the header address and attribute phases, as well as for burst and DWORD transaction data phases. The error correction code check-bits are inserted into unused attribute, clock phase, reserved, or reserved drive high portions of the AD and/or C/BE# lanes of the PCI-X phases.

摘要翻译： 用于计算机系统中的外设组件互连总线系统（PCI-X）扩展的纠错码机制与完整的PCI协议完全向后兼容。 可以插入纠错码校验位，以提供头部地址和属性相位以及突发和DWORD事务数据阶段的纠错能力。 错误校正码校验位被插入到PCI-X阶段的AD和/或C / BE＃通道的未使用的属性，时钟相位，保留或保留的驱动器高部分中。

公开(公告)号：US06892259B2

公开(公告)日：2005-05-10

申请号：US09967608

申请日：2001-09-29

申请人： Alan L. Goodrum ,  Dwight D. Riley

发明人： Alan L. Goodrum ,  Dwight D. Riley

IPC分类号： G06F13/364 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F13/364

摘要： A target device in a computer bus system allocates resources by selecting a priority requester for allocation of scarce resources. In a non-bus arbiter configuration, the first initiator device to receive a retry response to a transaction request after the resources are exhausted is designated as a priority requester. In a bus arbiter configuration, the priority requester is chosen on a round-robin basis from initiator devices that received a retry response to the initiator's most recent transaction request. If only one resource is available when an initiator sends a transaction request, the initiator receives a retry response unless the initiator is the priority requester.

摘要翻译： 计算机总线系统中的目标设备通过选择用于分配稀缺资源的优先级请求者来分配资源。 在非总线仲裁器配置中，在资源耗尽之后接收对事务请求的重试响应的第一启动器设备被指定为优先级请求器。 在总线仲裁器配置中，优先级请求者是从接收到对发起者最近的事务请求的重试响应的发起者设备的循环选择的。 如果发起方发送事务请求只有一个资源可用，则启动器将接收重试响应，除非启动器是优先级请求者。

公开(公告)号：US06871248B2

公开(公告)日：2005-03-22

申请号：US09967606

申请日：2001-09-29

申请人： Dwight D. Riley

发明人： Dwight D. Riley

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  H04J3/16 ,  H04J3/22

CPC分类号： G06F13/405

摘要： An isochronous channel is configured on an interconnect bus between a first device and a second device. A first device requests an isochronous channel, required bandwidth, and a required service window size. If a service window of the required size at the required bandwidth is available, an isochronous bus controller sends the request to the second device. If the second device has a service window of the required size at the required, it accepts the isochronous channel request. The isochronous bus controller can be a collection of isochronous controllers, each controlling a subset of the interconnect bus. The isochronous bus controller then allocates bandwidth to the first device, notifying the first device to begin generating isochronous transactions, controlling access to the bus to ensure the first device does not exceed the bandwidth allocation. Further, the isochronous bus controller terminates the isochronous channel, if the first device stops sending isochronous transactions.

摘要翻译： 在第一设备和第二设备之间的互连总线上配置同步信道。 第一个设备请求同步信道，所需带宽和所需的服务窗口大小。 如果所需带宽的所需大小的服务窗口可用，则同步总线控制器将请求发送到第二设备。 如果第二个设备具有所需大小的服务窗口，则接受同步信道请求。 同步总线控制器可以是同步控制器的集合，每个控制器控制互连总线的子集。 等时总线控制器然后将带宽分配给第一设备，通知第一设备开始生成等时事务，控制对总线的访问以确保第一设备不超过带宽分配。 此外，等时总线控制器终止同步信道，如果第一设备停止发送同步事务。

公开(公告)号：US5937173A

公开(公告)日：1999-08-10

申请号：US873420

申请日：1997-06-12

申请人： Sompong Paul Olarig ,  Dwight D. Riley ,  Ronald Timothy Horan

发明人： Sompong Paul Olarig ,  Dwight D. Riley ,  Ronald Timothy Horan

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027

摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect ("RegPCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

摘要翻译： 在可以被配置为加速图形端口（“AGP”）总线与主机与存储器总线之间的桥接的计算机系统中提供了多用途核心逻辑芯片组，作为附加的注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。 多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。 多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。 可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）的类型。 也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。

公开(公告)号：US09037768B2

公开(公告)日：2015-05-19

申请号：US12937685

申请日：2008-04-28

申请人： Hubert E. Brinkmann ,  Paul V. Brownell ,  David L. Matthews ,  Dwight D. Riley

发明人： Hubert E. Brinkmann ,  Paul V. Brownell ,  David L. Matthews ,  Dwight D. Riley

IPC分类号： G06F13/24 ,  G06F9/455

CPC分类号： G06F13/24 ,  G06F9/45558 ,  G06F2009/45579 ,  G06F2213/0026

摘要： Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

摘要翻译： 本发明的实施例涉及用于代表包括I / O设备控制器的中断产生设备虚拟化中断模式的方法，使得缺少较旧的中断模式的较新的中断产生设备可以在继续依赖的系统中使用 在较老的中断模式下。 在本发明的一个实施例中，改进了PCIe交换机或基于PCIe的主桥，或者引入了新的组件来提供代表虚拟中断模式的中断模式虚拟化功能或虚拟中断模式接口 诸如I / O设备控制器的中断产生设备到操作系统，BIOS层以及与I / O设备控制器通信的其他组件。

公开(公告)号：US08224987B2

公开(公告)日：2012-07-17

申请号：US11078851

申请日：2005-03-11

申请人： Dwight D. Riley

发明人： Dwight D. Riley

IPC分类号： G06F15/173

CPC分类号： H04L12/28

摘要： A system and method for a hierarchical interconnect network. Some illustrative embodiments comprise a network switch comprising a plurality of ports each adapted to couple to other devices external to the network switch as part of an interconnect network (the interconnect network comprises an inverted tree structure that originates with a root bus), a controller coupled to the plurality of ports (the controller defines an active path through the network switch, the active path follows the inverted tree structure), and a memory coupled to the controller (the memory comprising routing information). The controller uses the routing information to identify an alternate path through the network switch. At least part of the alternate path does not follow the inverted tree structure.

摘要翻译： 一种用于分层互连网络的系统和方法。 一些说明性实施例包括网络交换机，其包括多个端口，每个端口适于耦合到作为互连网络的一部分的网络交换机外部的其他设备（互连网络包括由根总线发起的反向树结构），控制器耦合 （控制器定义通过网络交换机的活动路径，主动路径遵循反向树结构），以及耦合到控制器（存储器包括路由信息）的存储器。 控制器使用路由信息来标识通过网络交换机的备用路径。 备用路径的至少一部分不遵循反向树结构。

公开(公告)号：US20110047309A1

公开(公告)日：2011-02-24

申请号：US12937685

申请日：2008-04-28

申请人： Hubert E. Brinkmann ,  Paul V. Brownell ,  David L. Mattews ,  Dwight D. Riley

发明人： Hubert E. Brinkmann ,  Paul V. Brownell ,  David L. Mattews ,  Dwight D. Riley

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/45558 ,  G06F2009/45579 ,  G06F2213/0026

摘要： Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

摘要翻译： 本发明的实施例涉及用于代表包括I / O设备控制器的中断产生设备虚拟化中断模式的方法，使得缺少较旧的中断模式的较新的中断产生设备可以在继续依赖的系统中使用 在较老的中断模式下。 在本发明的一个实施例中，改进了PCIe交换机或基于PCIe的主桥，或者引入了新的组件来提供代表虚拟中断模式的中断模式虚拟化功能或虚拟中断模式接口 诸如I / O设备控制器的中断产生设备到操作系统，BIOS层以及与I / O设备控制器通信的其他组件。

公开(公告)号：US07876759B2

公开(公告)日：2011-01-25

申请号：US11775967

申请日：2007-07-11

申请人： Hahn Vo Norden ,  Hubert E. Brinkmann ,  Paul V. Brownell ,  Kenneth T. Chin ,  James Dinh ,  David L. Matthews ,  Dwight D. Riley

发明人： Hahn Vo Norden ,  Hubert E. Brinkmann ,  Paul V. Brownell ,  Kenneth T. Chin ,  James Dinh ,  David L. Matthews ,  Dwight D. Riley

IPC分类号： H04L12/56

CPC分类号： H04L47/10 ,  H04L47/32 ,  H04L47/39

摘要： A system is provided comprising a fabric coupling together a plurality of computing devices, wherein the fabric transfers a stream of packets between the computing devices. Each computing device comprises a Quality of Service (“QOS”) filter that monitors incoming packets to filter out packets of a maintenance type and permit transfer of packets of a transaction type.

摘要翻译： 提供了一种系统，其包括将多个计算设备耦合在一起的结构，其中该结构在计算设备之间传送分组流。 每个计算设备包括服务质量（“QOS”）过滤器，其监视进入的分组以过滤维护类型的分组并且允许传输交易类型的分组。

公开(公告)号：US07110413B2

公开(公告)日：2006-09-19

申请号：US10038793

申请日：2001-12-31

申请人： Dwight D. Riley

发明人： Dwight D. Riley

IPC分类号： H04L12/28

CPC分类号： H04L12/46 ,  H04L12/4625

摘要： An interconnect switch provides full PCI compatibility while increasing performance via concurrency. The switch contains a primary bridge on a primary port. Secondary ports of the switch can be connected to secondary bridges and end devices. The switch can shadow registers associated with the secondary bridges. A transaction with a target address behind a secondary bridge is directly routed to the secondary port associated with the secondary bridge, using the shadowed registers. A transaction with a target address not behind a secondary bridge is routed to each of the other secondary ports. The transaction can be broadcast to all of the non-bridge secondary ports or can be routed successively to each of the non-bridge secondary ports until accepted. A tuning process can use positive acknowledgment of a transaction by an end device connected to a secondary port to directly route similar transactions to the same secondary port.