公开(公告)号：US20160163964A1

公开(公告)日：2016-06-09

申请号：US15046483

申请日：2016-02-18

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract translation: 磁阻存储元件（例如，自旋转矩磁阻存储元件）包括固定磁性层，具有垂直磁各向异性的自由磁性层和设置在固定磁性层和自由磁性层之间的第一电介质。 第一电介质的第一表面与自由磁性层的第一表面接触。 磁阻存储元件还包括第二电介质，其具有与自由磁性层的第二表面接触的第一表面，包括导电材料的导体以及设置在第二电介质和导体之间的电极。 电极包括：（i）具有与第二电介质的第二表面接触的表面的非铁磁部分，和（ii）第二部分，其包括设置在第二电介质的非铁磁部分之间的至少一个铁磁材料 电极和导体。

公开(公告)号：US09293698B2

公开(公告)日：2016-03-22

申请号：US14701831

申请日：2015-05-01

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jason Janesky ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  B82Y10/00

CPC classification number: H01L43/02 ,  B82Y10/00 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10S977/935

Abstract: In one aspect, the present inventions are directed to a magnetoresistive structure having a tunnel junction, and a process for manufacturing such a structure. The tunnel barrier may be formed between a free layer and a fixed layer in a plurality of repeating process of depositing a metal material and oxidizing at least a portion of the metal material. Where the tunnel barrier is formed by deposition of at least three metal materials interceded by an associated oxidization thereof, the oxidation dose associated with the second metal material may be greater than the oxidation doses associated with the first and third metal materials. In certain embodiments, the fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.

Abstract translation: 一方面，本发明涉及具有隧道结的磁阻结构，以及制造这种结构的方法。 可以在沉积金属材料和氧化至少一部分金属材料的多个重复工艺中，在自由层和固定层之间形成隧道势垒。 在通过沉积由其相关氧化作用介入的至少三种金属材料形成隧道势垒的地方，与第二金属材料相关的氧化剂量可能大于与第一和第三金属材料相关联的氧化剂量。 在某些实施例中，固定层可以在两层铁磁材料之间的固定层中包括不连续的金属层，例如Ta。

公开(公告)号：US20160013401A1

公开(公告)日：2016-01-14

申请号：US14860657

申请日：2015-09-21

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive memory element (for example, a spin-torque magnetoresistive memory element), includes first and second dielectric layers, wherein at least one of the dielectric layers is a magnetic tunnel junction. The memory element also includes a free magnetic layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer. The free magnetic layer, which is disposed between the first and second dielectric layers, includes (i) a first high-iron interface region located along the first surface of the free magnetic layer, wherein the first high-iron interface region has at least 50% iron by atomic composition, and (ii) a first layer of ferromagnetic material adjacent to the first high-iron interface region, the first high-iron interface region between the first layer of ferromagnetic material and the first surface of the free magnetic layer.

Abstract translation: 磁阻存储元件（例如，自旋扭矩磁阻存储元件）包括第一和第二电介质层，其中至少一个电介质层是磁性隧道结。 存储元件还包括具有与第一介电层接触的第一表面和与第二介电层接触的第二表面的自由磁性层。 设置在第一和第二电介质层之间的自由磁性层包括（i）沿着自由磁性层的第一表面设置的第一高铁界面区域，其中第一高铁界面区域具有至少50 以及（ii）与第一高铁界面区域相邻的第一铁磁材料层，第一铁磁材料层与自由磁性层的第一表面之间的第一高铁界面区域。

公开(公告)号：US09136464B1

公开(公告)日：2015-09-15

申请号：US14037087

申请日：2013-09-25

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jason Janesky ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/02 ,  B82Y10/00

CPC classification number: H01L43/02 ,  B82Y10/00 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10S977/935

Abstract: An MRAM device, and a process for manufacturing the device, provides improved breakdown distributions, a reduced number of bits with a low breakdown voltage, and an increased MR, thereby improving reliability, manufacturability, and error-free operation. A tunnel barrier is formed between a free layer and a fixed layer in three repeating steps of forming a metal material, interceded by oxidizing each of the metal materials. The oxidization of the third metal material is greater than the dose of the first metal, but less than the dose of the second metal. The fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.

Abstract translation: MRAM器件以及用于制造器件的工艺提供了改进的击穿分布，具有低击穿电压的位数减少以及增加的MR，从而提高了可靠性，可制造性和无错误操作。 在自由层和固定层之间形成隧道势垒，在三个重复步骤中形成金属材料，通过氧化每种金属材料进行交换。 第三金属材料的氧化大于第一金属的剂量，但小于第二金属的剂量。 固定层可以在两层铁磁材料之间的固定层中包括不连续的金属层，例如Ta。

公开(公告)号：US09093637B2

公开(公告)日：2015-07-28

申请号：US14303200

申请日：2014-06-12

Applicant: Everspin Technologies, Inc.

Inventor： Srinivas V. Pietambaram ,  Bengt J. Akerman ,  Renu Whig ,  Jason A. Janesky ,  Nicholas D. Rizzo ,  Jon M. Slaughter

IPC: H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10

Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.

Abstract translation: MRAM位（10）包括自由磁区（15），包括反铁磁材料的固定磁区（17）和隧道势垒（16），其包括位于自由磁区（15）和固定 磁区（17）。 MRAM位（10）通过使用高Hk（单轴各向异性），高Hsat（饱和磁场）和显示明确定义的理想软磁性质的组合，包括表现出明确的高Hflop的固定磁区，避免了钉扎层 容易和坚硬的轴。

公开(公告)号：US20140159179A1

公开(公告)日：2014-06-12

申请号：US14168095

申请日：2014-01-30

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Jijun Sun ,  Phillip Mather ,  Srinivas Pietambaram ,  Jon Slaughter ,  Renu Whig ,  Nicholas Rizzo

IPC: H01L43/10 ,  H01L43/12

CPC classification number: H01L43/10 ,  G01R33/098 ,  H01L43/12 ,  Y10T29/49117

Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.

Abstract translation: 提供传感器和制造工艺，用于形成具有基本上正交的磁化方向的参考层，具有零偏移并具有小的补偿角。 示例性实施例包括基于磁阻薄膜的磁场传感器的传感器层堆叠，传感器层堆叠包括钉扎层; 包括在钉扎层上的无定形材料层的钉扎层和在非晶材料层上的第一层结晶材料; 在被钉扎层上的非磁性耦合层; 在非磁耦合层上的固定层; 固定层上的隧道势垒; 以及在非磁性中间层上的感测层。 另一个实施例包括传感器层堆叠，其中包括由非晶层隔开的两个结晶层的钉扎层。

公开(公告)号：US20140138346A1

公开(公告)日：2014-05-22

申请号：US13972637

申请日：2013-08-21

Applicant: EverSpin Technologies, Inc.

Inventor： Renu Whig ,  Philip Mather ,  Kenneth Smith ,  Sanjeev Aggarwal ,  Jon Slaughter ,  Nicholas Rizzo

IPC: H01L43/12 ,  G01R33/09

CPC classification number: H01L43/12 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract translation: 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。

公开(公告)号：US08647891B2

公开(公告)日：2014-02-11

申请号：US13909622

申请日：2013-06-04

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Phillip Mather ,  Srinivas Pietambaram ,  Jon Slaughter ,  Renu Whig ,  Nicholas Rizzo

IPC: H01L21/00

CPC classification number: H01L43/10 ,  G01R33/098 ,  H01L43/12 ,  Y10T29/49117

Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.

Abstract translation: 提供传感器和制造工艺，用于形成具有基本上正交的磁化方向的参考层，具有零偏移并具有小的补偿角。 示例性实施例包括基于磁阻薄膜的磁场传感器的传感器层堆叠，传感器层堆叠包括钉扎层; 包括在钉扎层上的无定形材料层的钉扎层和在非晶材料层上的第一层结晶材料; 在被钉扎层上的非磁性耦合层; 在非磁耦合层上的固定层; 固定层上的隧道势垒; 以及在非磁性中间层上的感测层。 另一个实施例包括传感器层堆叠，其中包括由非晶层隔开的两个结晶层的钉扎层。

公开(公告)号：US10692926B2

公开(公告)日：2020-06-23

申请号：US16601848

申请日：2019-10-15

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Sanjeev Aggarwal ,  Han-Jong Chia ,  Jon M. Slaughter ,  Renu Whig

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  G11B5/39 ,  H01L43/10

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

公开(公告)号：US10516103B1

公开(公告)日：2019-12-24

申请号：US16551952

申请日：2019-08-27

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L21/00 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.