利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

107 条记录 (耗时 0.042 秒)

    Wiring optimizations for power
    31.
    发明授权
    Wiring optimizations for power 有权
    电力接线优化

    公开(公告)号：US07469395B2

    公开(公告)日：2008-12-23

    申请号：US11952544

    申请日：2007-12-07

    申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

    发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

    摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

    摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有每时钟周期相同方向的切换概率phiSD，其不小于预先选择的最小相同方向切换概率phiSD，MIN或具有不小于a的每个时钟周期的相反方向切换概率phiOD 预先选择的最小相反方向切换概率phiOD，MIN。 第一线和第二线满足涉及LCOMMON和WSPACING的至少一个数学关系，其中WSPACING被定义为第一线和第二线之间的间隔，并且LCOMMON被定义为第一线和第二线的公共行程长度 线。

    Use of redundant routes to increase the yield and reliability of a VLSI layout
    32.
    发明授权
    Use of redundant routes to increase the yield and reliability of a VLSI layout 有权
    使用冗余路由来提高VLSI布局的收益和可靠性

    公开(公告)号：US07308669B2

    公开(公告)日：2007-12-11

    申请号：US10908593

    申请日：2005-05-18

    申请人： Markus T. Buehler ,  John M. Cohn ,  David J. Hathaway ,  Jason D. Hibbeler ,  Juergen Koehl

    发明人： Markus T. Buehler ,  John M. Cohn ,  David J. Hathaway ,  Jason D. Hibbeler ,  Juergen Koehl

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5068

    摘要： Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

    摘要翻译： 公开了一种将冗余路径插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于在连接两个元件的第一路径中识别单个通孔的方法，确定替代路线是否可用于连接两个元件（不同于冗余通路），以及用于将第二路径插入到可用替代 路线。 第一和第二路径的组合提供了比单独插入冗余通道更大的冗余。 更重要的是，当拥塞阻止冗余通道被插入邻近单个通道时，这种冗余路径提供了冗余。 如果用于形成第二路径的所有附加通孔都可以是冗余的，则该方法的实施例还包括去除单个通孔和任何冗余线段。

    Method of optimizing and analyzing selected portions of a digital integrated circuit
    33.
    发明授权
    Method of optimizing and analyzing selected portions of a digital integrated circuit 有权
    优化和分析数字集成电路的选定部分的方法

    公开(公告)号：US07010763B2

    公开(公告)日：2006-03-07

    申请号：US10436213

    申请日：2003-05-12

    申请人： David J. Hathaway ,  Lawrence Kenneth Lange ,  Chandramouli Visweswariah ,  Patrick M. Williams

    发明人： David J. Hathaway ,  Lawrence Kenneth Lange ,  Chandramouli Visweswariah ,  Patrick M. Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Disclosed is a method for achieving timing closure in the design of a digital integrated circuit or system by selecting portions of the circuit or system to be optimized and portions of the circuit or system in which the effects of such optimization are to be analyzed during the optimization process. Optimized portions will include gates whose design parameters are to be changed, a first analyzed portion includes gates whose delays and edge slews are to be recomputed, and a second analyzed portion includes gates whose ATs and RATs are to be recomputed during optimization. Constraints are imposed at selected boundaries between these portions to prevent unwanted propagation of timing information and to ensure the validity of timing values used during optimization. Through this selection, the size of the problem posed to the underlying optimization method will be reduced, allowing larger circuits or systems to be optimized and allowing optimization to be performed more quickly.

    摘要翻译： 公开了一种在数字集成电路或系统的设计中实现定时闭合的方法，通过选择要优化的电路或系统的部分以及在优化期间分析这种优化的影响的电路或系统的部分 处理。 优化部分将包括其设计参数将被改变的门，第一分析部分包括要重新计算其延迟和边缘电压的门，并且第二分析部分包括在优化期间重新计算其AT和RAT的门。 在这些部分之间的选定边界施加约束，以防止定时信息的不期望的传播，并确保优化期间使用的定时值的有效性。 通过这种选择，将降低对基础优化方法造成的问题的大小，从而允许更大的电路或系统被优化，并允许更快地执行优化。

    Method for distributing a set of objects in computer application
    34.
    发明授权
    Method for distributing a set of objects in computer application 失效
    在计算机应用程序中分发一组对象的方法

    公开(公告)号：US06778999B2

    公开(公告)日：2004-08-17

    申请号：US09976698

    申请日：2001-10-12

    申请人： David J. Hathaway

    发明人： David J. Hathaway

    IPC分类号： G06F1730

    CPC分类号： G06F17/5072 ,  G06F17/5045 ,  Y10S707/959 ,  Y10S707/99944 ,  Y10S707/99945

    摘要： A method of determining redistribution of objects among three or more containers in a network comprises determining an initial set of objects in each of the containers, identifying neighboring pairs of containers, determining a cost of moving objects between each of the neighboring pairs of containers, determining a desired change in occupancy of each container, and subsequently determining a desired total size of a set of objects to be moved between each identified neighboring pair of containers by solving a set of simultaneous linear equations. The objects are redistributed among the neighboring pairs of containers in accordance with the solution. The objects may be clock sinks and the containers clock nets on a chip, or the objects may be circuits to be placed in an integrated circuit and the containers regions of the chip, or the objects may be data files and the containers individual network server computers.

    摘要翻译： 确定网络中的三个或更多个容器之间的对象再分配的方法包括确定每个容器中的对象的初始集合，识别相邻的容器对，确定在每个相邻容器对之间移动对象的成本，确定 每个容器的占有率的期望变化，并且随后通过求解一组联立线性方程来确定要在每个识别的相邻容器对之间移动的一组物体的期望总体尺寸。 根据解决方案，对象在相邻的容器对之间重新分配。 对象可以是时钟汇集器和芯片上的容器时钟网络，或者对象可以是被放置在集成电路中的电路，并且芯片的容器区域或对象可以是数据文件和容器单个网络服务器计算机 。

    Distributed static timing analysis
    36.
    发明授权
    Distributed static timing analysis 失效
    分布式静态时序分析

    公开(公告)号：US06202192B1

    公开(公告)日：2001-03-13

    申请号：US09004813

    申请日：1998-01-09

    申请人： Wilm E. Donath ,  David J. Hathaway

    发明人： Wilm E. Donath ,  David J. Hathaway

    IPC分类号： G06F1750

    CPC分类号： G06F17/5031

    摘要： A method of distributed timing analysis for a network which has been partitioned into at least two partitions, with each partition being assigned to a separate timing analysis process which communicates with the other processes is provided. A depth first search is performed by the process assigned to the partition in which the node for which timing information is desired is located. When the depth first search encounters a node for which a timing value is required which is located in another partition, a request is immediately sent to the process corresponding to that partition for the required timing information. When the request for timing information from the other partition is answered, the associated node is placed in the propagation queue. Also, as a node is processed, successor nodes which have had their predecessors processed are added to the propagation queue. The nodes in the propagation queue are processes and timing values are computed. When there are no nodes in the propagation queue, global loop detection is performed. Additionally, incremental timing updates are performed when a change is made in the network.

    摘要翻译： 一种分布在至少两个分区中的网络的分布式时序分析方法，其中每个分区分配给与其他进程进行通信的单独的定时分析过程。 通过分配给期望定时信息的节点所在的分区的处理来执行深度优先搜索。 当深度第一次搜索遇到位于另一个分区中需要定时值的节点时，立即将请求发送到与该分区相对应的处理所需的定时信息。 当来自其他分区的定时信息的请求被应答时，相关联的节点被放置在传播队列中。 另外，当处理节点时，将其前辈处理的后继节点添加到传播队列中。 传播队列中的节点是进程，计算定时值。 当传播队列中没有节点时，执行全局环路检测。 此外，当在网络中进行更改时，会执行增量时序更新。

    Incremental timing analysis
    37.
    发明授权
    Incremental timing analysis 失效
    增量时序分析

    公开(公告)号：US5508937A

    公开(公告)日：1996-04-16

    申请号：US49699

    申请日：1993-04-16

    申请人： Richard P. Abato ,  Anthony D. Drumm ,  David J. Hathaway ,  Lukas P. P. P. van Ginneken

    发明人： Richard P. Abato ,  Anthony D. Drumm ,  David J. Hathaway ,  Lukas P. P. P. van Ginneken

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Incremental timing analyzer for selectively performing timing analysis on a revised electronic circuit design resulting from one or more modifications to an initial electronic circuit design having input nodes, output nodes, and active elements electrically connected therebetween in a set of signal paths interconnected by a plurality of nodes. Each signal path has a timing delay associated therewith. Data is recorded representative of the modification's affect on relative timing values for a set of signals propagated through the circuit design. The recorded data includes a leftmost frontier of change in relative timing values and a rightmost frontier of change in relative timing values. Upon presentation of a specific timing analysis request, incremental timing analysis on the selected portion of the modified electronic circuit design is conducted employing the recorded frontiers of change to limit the timing value analysis. The concepts presented may be used for incremental recalculation of any signal value propagated forward or backward through a logic network.

    摘要翻译： 增量定时分析器，用于选择性地对经修改的电子电路设计进行定时分析，所述修正的电子电路设计是由具有输入节点，输出节点和电连接在其间的有源元件的初始电子电路设计的一个或多个修改而导致的， 节点。 每个信号路径具有与之相关的定时延迟。 记录数据表示修改对通过电路设计传播的一组信号的相对定时值的影响。 所记录的数据包括相对定时值变化的最左边界和相对定时值的最右边改变的边界。 在呈现特定的时间分析请求时，利用所记录的改变的边界进行修改的电子电路设计的所选部分的增量定时分析，以限制时序值分析。 所呈现的概念可用于对通过逻辑网络向前或向后传播的任何信号值的增量重新计算。

    Decentralized dynamically scheduled parallel static timing analysis
    38.
    发明授权
    Decentralized dynamically scheduled parallel static timing analysis 失效
    分散式动态调度并行静态时序分析

    公开(公告)号：US08775988B2

    公开(公告)日：2014-07-08

    申请号：US13150445

    申请日：2011-06-01

    申请人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

    发明人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/504 ,  G06F2217/84

    摘要： A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.

    摘要翻译： 一种用于执行并行静态时序分析的方法，其中多个进程独立地更新时序图，而不需要通过中央协调器模块进行通信。 本地处理队列用于减少锁定开销，而不会导致过大的负载不平衡。 对由多个互连节点形成的时序图表示的电路设计进行并行分析，该方法包括：使用计算机创建准备处理独立节点的共享工作队列; 将独立节点从工作队列分配到至少两个并行计算过程，同时执行其节点分析计算; 以及通过更新从所述节点分析获得的经处理的独立节点的值来修改所述电路设计，所述至少两个并行计算处理独立地更新所述共享工作队列以处理新的多个独立节点。