利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

48 条记录 (耗时 0.024 秒)

    PROCESS IDENTIFIER-BASED CACHE DATA TRANSFER
    31.
    发明申请
    PROCESS IDENTIFIER-BASED CACHE DATA TRANSFER 有权
    基于过程识别器的高速缓存数据传输

    公开(公告)号：US20130332670A1

    公开(公告)日：2013-12-12

    申请号：US13493636

    申请日：2012-06-11

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    IPC分类号： G06F12/08

    CPC分类号： G06F17/30982 ,  G06F12/0817 ,  G06F12/12

    摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.

    摘要翻译： 本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。 本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。 本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。 本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。 本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

    Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data
    34.
    发明授权
    Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data 有权
    用于打包十进制数据的存储预对齐和EBCDIC，ASCII和unicode基本拉丁转换

    公开(公告)号：US07167968B2

    公开(公告)日：2007-01-23

    申请号：US10834637

    申请日：2004-04-29

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Mark A. Check ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Frank Tanzi

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Mark A. Check ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Frank Tanzi

    IPC分类号： G06F12/06

    CPC分类号： G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3824 ,  G06F12/0886

    摘要： A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.

    摘要翻译： 在指令执行期间预先对准用于存储的数据的方法通过消除数据对准所需的周期来提高性能。 该方法可以在ASCII和Packed Decimal格式之间以及Unicode Basic Latin和Packed Decimal格式之间转换数据。 转换为打包十进制硬件需要十进制格式，用于生成十进制结果的微处理器。 从包装十进制转换为ASCII和Unicode基本拉丁文需要以应用程序所需的格式报告十进制算术结果。 为了进一步提高性能，利用固定点单元（FXU）中的所有可用写入端口来减少存储结果所需的周期数。 为了防止数据获取未使用的目标数据缓慢的指令执行，目标位置被测试存储访问异常，但是这些操作数的数据实际上并没有被提取。 从FXU到操作数缓冲区的单个读取请求在单个周期中有效读取整个目标地址（最多8个双字的数据）。

    Decimal multiplication for superscaler processors
    35.
    发明授权
    Decimal multiplication for superscaler processors 失效
    超标量处理器的十进制乘法

    公开(公告)号：US07167889B2

    公开(公告)日：2007-01-23

    申请号：US10436392

    申请日：2003-05-12

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr.

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr.

    IPC分类号： G06F7/523

    CPC分类号： G06F9/3001 ,  G06F7/496

    摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.

    摘要翻译： 一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。 部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍 乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

    VERIFICATION USING OPCODE COMPARE
    36.
    发明申请
    VERIFICATION USING OPCODE COMPARE 有权
    使用操作码比较验证

    公开(公告)号：US20110320783A1

    公开(公告)日：2011-12-29

    申请号：US12822417

    申请日：2010-06-24

    申请人： Christopher A. Krygowski ,  Michael P. Mullen ,  Timothy J. Slegel ,  Kai Weber

    发明人： Christopher A. Krygowski ,  Michael P. Mullen ,  Timothy J. Slegel ,  Kai Weber

    IPC分类号： G06F9/30

    CPC分类号： G06F17/504 ,  G06F9/30 ,  G06F11/3636 ,  G06F11/3648

    摘要： A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware.

    摘要翻译： 提供了一种验证方法，包括在预定义的程序中随机选择硬件执行指令以强制运行代码比较，根据所选择的指令确定相应操作码的标识，并初始化操作码比较逻辑，将所选指令陷入固件并创建固件 启动硬件验证的性能，并重新启动硬件验证的性能。

    Method, system, and computer program product for out of order instruction address stride prefetch performance verification
    40.
    发明授权
    Method, system, and computer program product for out of order instruction address stride prefetch performance verification 有权
    方法，系统和计算机程序产品，用于无序指令地址步进预取性能验证

    公开(公告)号：US07996203B2

    公开(公告)日：2011-08-09

    申请号：US12023457

    申请日：2008-01-31

    申请人： Wei-Yi Xiao ,  Dean G. Bair ,  Christopher A. Krygowski ,  Chung-Lung K. Shum

    发明人： Wei-Yi Xiao ,  Dean G. Bair ,  Christopher A. Krygowski ,  Chung-Lung K. Shum

    IPC分类号： G06F9/44 ,  G06F13/10 ,  G06F13/12

    CPC分类号： G06F9/3851 ,  G06F11/3457 ,  G06F12/0862 ,  G06F2201/885 ,  G06F2212/6026

    摘要： A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides.

    摘要翻译： 提供了一种方法，系统和计算机程序产品，用于在具有多于一个级别的高速缓存层级的处理器设计中验证无序指令地址（IA）跨步预取性能。 产生多个指令流，并将指令循环回相应的指令地址。 将多个指令流调度到处理器和仿真应用程序进行处理。 当调度特定指令时，将特定指令的指令地址和操作数地址记录在队列中。 监视处理器以确定处理器是否根据仿真应用执行提取和预取命令。 检查是否为具有三个或更多步长的指令发出预取命令。