公开(公告)号：US06839818B2

公开(公告)日：2005-01-04

申请号：US10036088

申请日：2001-12-28

Applicant: Roberto Gastaldi ,  Gianbattsista Lo Giudice ,  Marco Pasotti ,  Federico Pio

Inventor： Roberto Gastaldi ,  Gianbattsista Lo Giudice ,  Marco Pasotti ,  Federico Pio

IPC: G11C16/10 ,  G06F12/00

CPC classification number: G11C16/102

Abstract: An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify the data held therein is characterized in that, for each user memory location, there is a corresponding pair of physical memory locations in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.

Abstract translation: 一种可电气修改的非易失性半导体存储器，其包括多个用户存储器位置，其可以从存储器外部单独寻址以便读取和修改其中保存的数据，其特征在于，对于每个用户存储器位置， 存储器中的对应物理存储器位置对，其替代地假设有效存储器位置和非活动存储器位置的功能，所述活动存储器位置包含预先写入的数据和非活动存储器位置 可用于写入新的数据以替换以前写入的数据，以便在要求使用新数据替换以前的数据时，先前的数据保存在存储器中，直到新的数据被写入。

公开(公告)号：US06803630B2

公开(公告)日：2004-10-12

申请号：US10350745

申请日：2003-01-24

Applicant: Federico Pio ,  Enrico Gomiero ,  Paola Zuliani

Inventor： Federico Pio ,  Enrico Gomiero ,  Paola Zuliani

IPC: H01L2976

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase. This is achieved by providing respective adjusters connected between a program voltage generator and the cell matrix, or alternatively forming the bit switch element inside a well and the byte switch element directly in the substrate.

Abstract translation: 本发明涉及一种调整半导体非易失性存储器中擦除/编程电压的方法。 存储器由具有浮置栅极，控制栅极和漏极和源极端子的至少一个存储单元矩阵形成，并且由行和列中的字节组织，每个字节包括连接有相应控制栅极的一组单元 通过字节开关类型的选择元件彼此并行地连接到公共控制线，并且每个单元通过位开关类型的选择元件连接到相应的控制列。 有利地，为存储器单元的编程电压提供双重调整，由此在擦除阶段期间的编程电压可以比写入阶段期间的编程电压模数更高。 这通过提供连接在编程电压发生器和单元矩阵之间的相应调节器，或者可选地将阱内的位开关元件和字节开关元件直接放置在衬底中来实现。

公开(公告)号：US06737715B2

公开(公告)日：2004-05-18

申请号：US10090978

申请日：2002-03-04

Applicant: Federico Pio ,  Paola Zuliani

Inventor： Federico Pio ,  Paola Zuliani

IPC: H01L2976

CPC classification number: H01L29/1041 ,  H01L21/76202

Abstract: A field effect transistor having a variable doping profile is presented. The field effect transistor is integrated on a semiconductor substrate with a respective active area of the substrate including a source and drain region. A channel region is interposed between the source and drain regions and has a predefined nominal width. The effective width of the channel region is defined by a variable doping profile.

Abstract translation: 提出了具有可变掺杂分布的场效应晶体管。 场效应晶体管集成在具有源极和漏极区的衬底的相应有源区的半导体衬底上。 沟道区域介于源区和漏区之间并且具有预定义的标称宽度。 沟道区域的有效宽度由可变掺杂分布限定。

公开(公告)号：US06642582B1

公开(公告)日：2003-11-04

申请号：US09364023

申请日：1999-07-30

Applicant: Giovanna Dalla Libera ,  Federico Pio

Inventor： Giovanna Dalla Libera ,  Federico Pio

IPC: H01L2128

CPC classification number: H01L27/088 ,  H01L21/823475

Abstract: A circuit structure integrated in a semiconductor substrate comprises at least one pair of transistors each being formed each in a respective active area region and having a source region and a drain region, as well as a channel region intervening between the source and drain regions and being overlaid by a gate region. The gate regions are connected electrically together by an overlying conductive layer and respective contacts. The contacts between the gate regions and the conductive layer are formed above the active areas.

Abstract translation: 集成在半导体衬底中的电路结构包括至少一对晶体管，每个晶体管各自在相应的有源区域中形成，并且具有源极区和漏极区以及介于源极和漏极区之间的沟道区，并且是 由栅极区域覆盖。 栅极区域通过覆盖的导电层和相应的触点电连接在一起。 栅极区域和导电层之间的接触形成在有源区域上方。

公开(公告)号：US06462400B1

公开(公告)日：2002-10-08

申请号：US09483656

申请日：2000-01-14

Applicant: Federico Pio ,  Paola Zuliani ,  Lorenzo Fratin

Inventor： Federico Pio ,  Paola Zuliani ,  Lorenzo Fratin

IPC: H01L23544

CPC classification number: H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Chip Outline Band (COB) structure for an integrated circuit integrated in a semiconductor chip having a semiconductor substrate of a first conductivity type and biased at a common reference potential of the integrated circuit, the COB structure comprising a substantially annular region formed in the substrate along a periphery thereof, and at least one annular conductor region superimposed on and contacting the substantially annular region, wherein the substantially annular region is electrically connected at the common reference potential.

Abstract translation: 用于集成在具有第一导电类型的半导体衬底并被偏置在集成电路的公共参考电位的半导体芯片中的集成电路的芯片外形带（COB）结构，所述COB结构包括形成在衬底中的大致环形区域 其外围，以及叠加在基本环形区域上并接触大致环形区域的至少一个环形导体区域，其中大致环形区域以公共参考电位电连接。

公开(公告)号：US06268633B1

公开(公告)日：2001-07-31

申请号：US09222568

申请日：1998-12-28

Applicant: Federico Pio ,  Olivier Pizzuto

Inventor： Federico Pio ,  Olivier Pizzuto

IPC: H01L2976

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.

Abstract translation: 集成在具有第一类型导电性的半导体衬底中的电子器件的结构，其包括至少第一HV晶体管和至少第二LV晶体管，每个具有相应的栅极区域。 所述第一HV晶体管具有具有第二类型导电性的轻掺杂漏极和源极区，并且所述第二LV晶体管具有具有第二类型导电性的各自的漏极和源极区，每个包含与相应栅极区相邻的轻掺杂部分， 第二部分是更重掺杂的并且包括硅化物层。

公开(公告)号：US06215688B1

公开(公告)日：2001-04-10

申请号：US09364766

申请日：1999-07-30

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L21336

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

Abstract: An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.

公开(公告)号：US5894146A

公开(公告)日：1999-04-13

申请号：US607067

申请日：1996-02-26

Applicant: Federico Pio ,  Paola Paruzzi

Inventor： Federico Pio ,  Paola Paruzzi

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: A matrix of EEPROM memory cells having a double polysilicon level of MOS technology and being arranged into rows and columns is monolithically integrated on a substrate of semiconductor material. Each cell comprises, in series, a transistor of the floating gate type which includes two layers of polysilicon superposed on each other and separated by an intervening layer of a dielectric material, and a selection transistor having a gate which comprises a first layer of polysilicon. The gates of the selection transistors in one row of said matrix are connected electrically together by a selection line comprising a second layer of polysilicon overlying the first layer. The intermediate layer of dielectric material is also partly interposed between the first and second layers of polysilicon such that the two layers are in contact at at least one zone of said selection line. Preferably, the contact zone is formed over field oxide regions and is away from the edges of the selection line. The matrix can advantageously be fabricated by a process of the self-aligned type, without making the process any more complicated.

Abstract translation: 具有MOS技术的双重多晶硅级别并被布置成行和列的EEPROM存储单元的矩阵被单片地集成在半导体材料的衬底上。 每个单元串联包括浮置型晶体管，该晶体管包括彼此重叠并由介电材料的中间层隔开的两层多晶硅，以及选择晶体管，其具有包括第一多晶硅层的栅极。 所述矩阵的一行中的选择晶体管的栅极通过包括覆盖在第一层上的第二多晶硅层的选择线电连接。 电介质材料的中间层也部分插入第一和第二多晶硅层之间，使得两层在所述选择线的至少一个区域处接触。 优选地，接触区形成在场氧化物区域上并远离选择线的边缘。 该矩阵可以有利地通过自对准型的工艺制造，而不会使工艺变得更加复杂。

公开(公告)号：US08841649B2

公开(公告)日：2014-09-23

申请号：US13600699

申请日：2012-08-31

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L45/06 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/101 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

Abstract translation: 提供三维记忆阵列及其形成方法。 示例性三维存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部，使得 至少一个导电延伸部与多个第一导线中的至少一个的一部分相交。 存储元件材料围绕至少一个导电延伸部形成。 细胞选择材料形成在至少一个导电延伸部周围。

公开(公告)号：US08737138B2

公开(公告)日：2014-05-27

申请号：US12949728

申请日：2010-11-18

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C16/04 ,  G11C16/06 ,  G06F13/00

CPC classification number: G11C5/147 ,  G06F12/0246 ,  G06F21/60 ,  G06F2212/7204 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0063 ,  G11C14/009 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/107 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

Abstract: Subject matter disclosed herein relates to techniques to operate memory.

Abstract translation: 本文公开的主题涉及操作存储器的技术。