公开(公告)号：US10283372B2

公开(公告)日：2019-05-07

申请号：US15705956

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Mark V. Raymond ,  Errol Todd Ryan ,  Nicholas V. LiCausi

IPC: H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532

Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.

公开(公告)号：US10199264B2

公开(公告)日：2019-02-05

申请号：US15875212

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Roderick A. Augur ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.

公开(公告)号：US10199261B1

公开(公告)日：2019-02-05

申请号：US15653638

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： James McMahon ,  Ryan S. Smith ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  Xunyuan Zhang ,  Shao Beng Law

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.

公开(公告)号：US20190021176A1

公开(公告)日：2019-01-17

申请号：US15647400

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

公开(公告)号：US10163633B2

公开(公告)日：2018-12-25

申请号：US15457200

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao Beng Law ,  Xunyuan Zhang ,  Errol Todd Ryan ,  Nicholas LiCausi

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027

Abstract: Methods of forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with the opening in the patterned sacrificial layer. A metal layer is formed on an area of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

公开(公告)号：US10157833B1

公开(公告)日：2018-12-18

申请号：US15602801

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Dongfei Pei ,  Frank W. Mont

IPC: H01L29/40 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.

公开(公告)号：US20180308752A1

公开(公告)日：2018-10-25

申请号：US15494762

申请日：2017-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Sean X. Lin ,  Mark V. Raymond

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76895 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/535

Abstract: Interconnect structures and methods of forming interconnect structures. An opening is formed that penetrates from a top surface of a dielectric layer into the dielectric layer. A first conductor layer is conformally deposited with a uniform thickness on the dielectric layer surrounding the first opening. A second conductor layer is formed in a space inside the first opening that is interior of the first conductor layer. The first conductor layer and the second conductor layer collectively define a hybrid feature that is embedded in the dielectric layer.

公开(公告)号：US10079208B2

公开(公告)日：2018-09-18

申请号：US15221647

申请日：2016-07-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Moosung M. Chae

IPC: H01L23/528 ,  H01L29/45 ,  H01L29/40 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76883 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0883 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66568

Abstract: Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: providing a structure with: a conductive region, and an inter-level dielectric (ILD) material positioned on the conductive region, wherein the ILD material includes a contact opening to the conductive region; forming a doped metal layer within the contact opening such that the doped metal layer overlies the conductive region, wherein the doped metal layer includes a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material.

公开(公告)号：US09966338B1

公开(公告)日：2018-05-08

申请号：US15490181

申请日：2017-04-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Shao Beng Law

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76883 ,  H01L21/76804 ,  H01L21/7685

Abstract: Methods of forming self-aligned cuts and structures formed with self-aligned cuts. A dielectric layer is formed on a metal hardmask layer, and a mandrel is formed on the dielectric layer. A cut is formed that extends through the dielectric layer to the metal hardmask layer. A section of a metal layer is formed on an area of the metal hardmask layer exposed by the cut in the dielectric layer. After the metal layer is formed, a spacer is formed on a vertical sidewall of the mandrel.

公开(公告)号：US09859217B1

公开(公告)日：2018-01-02

申请号：US15614925

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengyu C. Niu ,  Vimal K. Kamineni ,  Mark V. Raymond ,  Xunyuan Zhang

IPC: H01L21/44 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535

Abstract: Integrated circuit (IC) structure embodiments and methods of forming them with middle of the line (MOL) contacts that incorporate a protective cap, which provides protection from damage during back end of the line (BEOL) processing. Each MOL contact has a main body in a lower portion of a contact opening. The main body has a liner (e.g., a titanium nitride layer) that lines the lower portion and a metal layer on the liner. The MOL contact also has a protective cap in an upper portion of the contact opening above the first metal layer and extending laterally over the liner to the sidewalls of the contact opening. The protective cap has an optional liner, which is different from the liner in the lower portion, and a metal layer, which is either the same or different than the metal in the main body.